PCI: Fix up L1SS capability for Intel Apollo Lake Root Port

On Google Coral and Reef family Chromebooks with Intel Apollo Lake SoC,
firmware clobbers the header of the L1 PM Substates capability and the
previous capability when returning from D3cold to D0.

Save those headers at enumeration-time and restore them at resume.

[bhelgaas: The main benefit is to make the lspci output after resume
correct.  Apparently there's little or no effect on power consumption.]

Link: https://lore.kernel.org/linux-pci/CAFJ_xbq0cxcH-cgpXLU4Mjk30+muWyWm1aUZGK7iG53yaLBaQg@mail.gmail.com/T/#u
Link: https://lore.kernel.org/r/20230411160213.4453-1-ron.lee@intel.com


Signed-off-by: Ron Lee <ron.lee@intel.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>