Commit 614b0590 authored by Matt Carlson's avatar Matt Carlson Committed by David S. Miller
Browse files

tg3: Enable PLL PD when CLKREQ disabled for 5717A0 



PCIe PLL power down cannot be used if CLKREQ is enabled because data
corruption will occur.  If CLKREQ is disabled though, enabling PCIE P1
PLL power-down saves some power.

Signed-off-by: default avatarMatt Carlson <mcarlson@broadcom.com>
Signed-off-by: default avatarMichael Chan <mchan@broadcom.com>
Reviewed-by: default avatarBenjamin Li <benli@broadcom.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 7981d6f6

drivers/net/tg3.c

+16 −0
Original line number Diff line number Diff line
@@ -7569,6 +7569,20 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy) 
		tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);

	}



	if (tp->tg3_flags3 & TG3_FLG3_L1PLLPD_EN) {

		u32 grc_mode = tr32(GRC_MODE);



		/* Access the lower 1K of PL PCIE block registers. */

		val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;

		tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL);



		val = tr32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1);

		tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1,

		     val | TG3_PCIE_PL_LO_PHYCTL1_L1PLLPD_EN);



		tw32(GRC_MODE, grc_mode);

	}



	/* This works around an issue with Athlon chipsets on

	 * B3 tigon3 silicon.  This bit has no effect on any

	 * other revision.  But do not set this on PCI Express
@@ -13096,6 +13110,8 @@ static int __devinit tg3_get_invariants(struct tg3 *tp) 
			    tp->pci_chip_rev_id == CHIPREV_ID_57780_A0 ||

			    tp->pci_chip_rev_id == CHIPREV_ID_57780_A1)

				tp->tg3_flags3 |= TG3_FLG3_CLKREQ_BUG;

		} else if (tp->pci_chip_rev_id == CHIPREV_ID_5717_A0) {

			tp->tg3_flags3 |= TG3_FLG3_L1PLLPD_EN;

		}

	} else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {

		tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;

drivers/net/tg3.h

+14 −0
Original line number Diff line number Diff line
@@ -1540,6 +1540,8 @@ 
#define  GRC_MODE_HOST_SENDBDS		0x00020000

#define  GRC_MODE_NO_TX_PHDR_CSUM	0x00100000

#define  GRC_MODE_NVRAM_WR_ENABLE	0x00200000

#define  GRC_MODE_PCIE_TL_SEL		0x00000000

#define  GRC_MODE_PCIE_PL_SEL		0x00400000

#define  GRC_MODE_NO_RX_PHDR_CSUM	0x00800000

#define  GRC_MODE_IRQ_ON_TX_CPU_ATTN	0x01000000

#define  GRC_MODE_IRQ_ON_RX_CPU_ATTN	0x02000000
@@ -1547,7 +1549,13 @@ 
#define  GRC_MODE_IRQ_ON_DMA_ATTN	0x08000000

#define  GRC_MODE_IRQ_ON_FLOW_ATTN	0x10000000

#define  GRC_MODE_4X_NIC_SEND_RINGS	0x20000000

#define  GRC_MODE_PCIE_DL_SEL		0x20000000

#define  GRC_MODE_MCAST_FRM_ENABLE	0x40000000

#define  GRC_MODE_PCIE_HI_1K_EN		0x80000000

#define  GRC_MODE_PCIE_PORT_MASK	(GRC_MODE_PCIE_TL_SEL | \

					 GRC_MODE_PCIE_PL_SEL | \

					 GRC_MODE_PCIE_DL_SEL | \

					 GRC_MODE_PCIE_HI_1K_EN)

#define GRC_MISC_CFG			0x00006804

#define  GRC_MISC_CFG_CORECLK_RESET	0x00000001

#define  GRC_MISC_CFG_PRESCALAR_MASK	0x000000fe
@@ -1801,6 +1809,11 @@ 
/* 0x7e74 --> 0x8000 unused */





/* Alternate PCIE definitions */

#define TG3_PCIE_TLDLPL_PORT		0x00007c00

#define TG3_PCIE_PL_LO_PHYCTL1		 0x00000004

#define TG3_PCIE_PL_LO_PHYCTL1_L1PLLPD_EN	  0x00001000



/* OTP bit definitions */

#define TG3_OTP_AGCTGT_MASK		0x000000e0

#define TG3_OTP_AGCTGT_SHIFT		1
@@ -2809,6 +2822,7 @@ struct tg3 { 
#define TG3_FLG3_40BIT_DMA_LIMIT_BUG	0x00100000

#define TG3_FLG3_SHORT_DMA_BUG		0x00200000

#define TG3_FLG3_USE_JUMBO_BDFLAG	0x00400000

#define TG3_FLG3_L1PLLPD_EN		0x00800000



	struct timer_list		timer;

	u16				timer_counter;