Loading drivers/scsi/qla2xxx/qla_dbg.c +32 −10 Original line number Original line Diff line number Diff line Loading @@ -277,9 +277,15 @@ qla24xx_dump_memory(struct qla_hw_data *ha, uint32_t *code_ram, if (rval != QLA_SUCCESS) if (rval != QLA_SUCCESS) return rval; return rval; set_bit(RISC_SRAM_DUMP_CMPL, &ha->fw_dump_cap_flags); /* External Memory. */ /* External Memory. */ return qla24xx_dump_ram(ha, 0x100000, *nxt, rval = qla24xx_dump_ram(ha, 0x100000, *nxt, ha->fw_memory_size - 0x100000 + 1, nxt); ha->fw_memory_size - 0x100000 + 1, nxt); if (rval == QLA_SUCCESS) set_bit(RISC_EXT_MEM_DUMP_CMPL, &ha->fw_dump_cap_flags); return rval; } } static uint32_t * static uint32_t * Loading @@ -297,12 +303,14 @@ qla24xx_read_window(struct device_reg_24xx __iomem *reg, uint32_t iobase, } } void void qla24xx_pause_risc(struct device_reg_24xx __iomem *reg) qla24xx_pause_risc(struct device_reg_24xx __iomem *reg, struct qla_hw_data *ha) { { WRT_REG_DWORD(®->hccr, HCCRX_SET_RISC_PAUSE); WRT_REG_DWORD(®->hccr, HCCRX_SET_RISC_PAUSE); /* 100 usec delay is sufficient enough for hardware to pause RISC */ /* 100 usec delay is sufficient enough for hardware to pause RISC */ udelay(100); udelay(100); if (RD_REG_DWORD(®->host_status) & HSRX_RISC_PAUSED) set_bit(RISC_PAUSE_CMPL, &ha->fw_dump_cap_flags); } } int int Loading @@ -325,6 +333,8 @@ qla24xx_soft_reset(struct qla_hw_data *ha) udelay(10); udelay(10); } } if (!(RD_REG_DWORD(®->ctrl_status) & CSRX_DMA_ACTIVE)) set_bit(DMA_SHUTDOWN_CMPL, &ha->fw_dump_cap_flags); WRT_REG_DWORD(®->ctrl_status, WRT_REG_DWORD(®->ctrl_status, CSRX_ISP_SOFT_RESET|CSRX_DMA_SHUTDOWN|MWB_4096_BYTES); CSRX_ISP_SOFT_RESET|CSRX_DMA_SHUTDOWN|MWB_4096_BYTES); Loading @@ -340,6 +350,9 @@ qla24xx_soft_reset(struct qla_hw_data *ha) udelay(10); udelay(10); } } if (!(RD_REG_DWORD(®->ctrl_status) & CSRX_ISP_SOFT_RESET)) set_bit(ISP_RESET_CMPL, &ha->fw_dump_cap_flags); WRT_REG_DWORD(®->hccr, HCCRX_CLR_RISC_RESET); WRT_REG_DWORD(®->hccr, HCCRX_CLR_RISC_RESET); RD_REG_DWORD(®->hccr); /* PCI Posting. */ RD_REG_DWORD(®->hccr); /* PCI Posting. */ Loading @@ -350,6 +363,8 @@ qla24xx_soft_reset(struct qla_hw_data *ha) else else rval = QLA_FUNCTION_TIMEOUT; rval = QLA_FUNCTION_TIMEOUT; } } if (rval == QLA_SUCCESS) set_bit(RISC_RDY_AFT_RESET, &ha->fw_dump_cap_flags); return rval; return rval; } } Loading Loading @@ -646,12 +661,13 @@ qla2xxx_dump_post_process(scsi_qla_host_t *vha, int rval) if (rval != QLA_SUCCESS) { if (rval != QLA_SUCCESS) { ql_log(ql_log_warn, vha, 0xd000, ql_log(ql_log_warn, vha, 0xd000, "Failed to dump firmware (%x).\n", rval); "Failed to dump firmware (%x), dump status flags (0x%lx).\n", rval, ha->fw_dump_cap_flags); ha->fw_dumped = 0; ha->fw_dumped = 0; } else { } else { ql_log(ql_log_info, vha, 0xd001, ql_log(ql_log_info, vha, 0xd001, "Firmware dump saved to temp buffer (%ld/%p).\n", "Firmware dump saved to temp buffer (%ld/%p), dump status flags (0x%lx).\n", vha->host_no, ha->fw_dump); vha->host_no, ha->fw_dump, ha->fw_dump_cap_flags); ha->fw_dumped = 1; ha->fw_dumped = 1; qla2x00_post_uevent_work(vha, QLA_UEVENT_CODE_FW_DUMP); qla2x00_post_uevent_work(vha, QLA_UEVENT_CODE_FW_DUMP); } } Loading Loading @@ -1040,6 +1056,7 @@ qla24xx_fw_dump(scsi_qla_host_t *vha, int hardware_locked) risc_address = ext_mem_cnt = 0; risc_address = ext_mem_cnt = 0; flags = 0; flags = 0; ha->fw_dump_cap_flags = 0; if (!hardware_locked) if (!hardware_locked) spin_lock_irqsave(&ha->hardware_lock, flags); spin_lock_irqsave(&ha->hardware_lock, flags); Loading @@ -1066,7 +1083,7 @@ qla24xx_fw_dump(scsi_qla_host_t *vha, int hardware_locked) * Pause RISC. No need to track timeout, as resetting the chip * Pause RISC. No need to track timeout, as resetting the chip * is the right approach incase of pause timeout * is the right approach incase of pause timeout */ */ qla24xx_pause_risc(reg); qla24xx_pause_risc(reg, ha); /* Host interface registers. */ /* Host interface registers. */ dmp_reg = ®->flash_addr; dmp_reg = ®->flash_addr; Loading Loading @@ -1290,6 +1307,7 @@ qla25xx_fw_dump(scsi_qla_host_t *vha, int hardware_locked) risc_address = ext_mem_cnt = 0; risc_address = ext_mem_cnt = 0; flags = 0; flags = 0; ha->fw_dump_cap_flags = 0; if (!hardware_locked) if (!hardware_locked) spin_lock_irqsave(&ha->hardware_lock, flags); spin_lock_irqsave(&ha->hardware_lock, flags); Loading Loading @@ -1317,7 +1335,7 @@ qla25xx_fw_dump(scsi_qla_host_t *vha, int hardware_locked) * Pause RISC. No need to track timeout, as resetting the chip * Pause RISC. No need to track timeout, as resetting the chip * is the right approach incase of pause timeout * is the right approach incase of pause timeout */ */ qla24xx_pause_risc(reg); qla24xx_pause_risc(reg, ha); /* Host/Risc registers. */ /* Host/Risc registers. */ iter_reg = fw->host_risc_reg; iter_reg = fw->host_risc_reg; Loading Loading @@ -1608,6 +1626,7 @@ qla81xx_fw_dump(scsi_qla_host_t *vha, int hardware_locked) risc_address = ext_mem_cnt = 0; risc_address = ext_mem_cnt = 0; flags = 0; flags = 0; ha->fw_dump_cap_flags = 0; if (!hardware_locked) if (!hardware_locked) spin_lock_irqsave(&ha->hardware_lock, flags); spin_lock_irqsave(&ha->hardware_lock, flags); Loading @@ -1634,7 +1653,7 @@ qla81xx_fw_dump(scsi_qla_host_t *vha, int hardware_locked) * Pause RISC. No need to track timeout, as resetting the chip * Pause RISC. No need to track timeout, as resetting the chip * is the right approach incase of pause timeout * is the right approach incase of pause timeout */ */ qla24xx_pause_risc(reg); qla24xx_pause_risc(reg, ha); /* Host/Risc registers. */ /* Host/Risc registers. */ iter_reg = fw->host_risc_reg; iter_reg = fw->host_risc_reg; Loading Loading @@ -1928,6 +1947,7 @@ qla83xx_fw_dump(scsi_qla_host_t *vha, int hardware_locked) risc_address = ext_mem_cnt = 0; risc_address = ext_mem_cnt = 0; flags = 0; flags = 0; ha->fw_dump_cap_flags = 0; if (!hardware_locked) if (!hardware_locked) spin_lock_irqsave(&ha->hardware_lock, flags); spin_lock_irqsave(&ha->hardware_lock, flags); Loading @@ -1953,7 +1973,7 @@ qla83xx_fw_dump(scsi_qla_host_t *vha, int hardware_locked) * Pause RISC. No need to track timeout, as resetting the chip * Pause RISC. No need to track timeout, as resetting the chip * is the right approach incase of pause timeout * is the right approach incase of pause timeout */ */ qla24xx_pause_risc(reg); qla24xx_pause_risc(reg, ha); WRT_REG_DWORD(®->iobase_addr, 0x6000); WRT_REG_DWORD(®->iobase_addr, 0x6000); dmp_reg = ®->iobase_window; dmp_reg = ®->iobase_window; Loading Loading @@ -2376,10 +2396,12 @@ qla83xx_fw_dump(scsi_qla_host_t *vha, int hardware_locked) nxt += sizeof(fw->code_ram); nxt += sizeof(fw->code_ram); nxt += (ha->fw_memory_size - 0x100000 + 1); nxt += (ha->fw_memory_size - 0x100000 + 1); goto copy_queue; goto copy_queue; } else } else { set_bit(RISC_RDY_AFT_RESET, &ha->fw_dump_cap_flags); ql_log(ql_log_warn, vha, 0xd010, ql_log(ql_log_warn, vha, 0xd010, "bigger hammer success?\n"); "bigger hammer success?\n"); } } } rval = qla24xx_dump_memory(ha, fw->code_ram, sizeof(fw->code_ram), rval = qla24xx_dump_memory(ha, fw->code_ram, sizeof(fw->code_ram), &nxt); &nxt); Loading drivers/scsi/qla2xxx/qla_dbg.h +2 −1 Original line number Original line Diff line number Diff line Loading @@ -353,5 +353,6 @@ extern int qla27xx_dump_mpi_ram(struct qla_hw_data *, uint32_t, uint32_t *, uint32_t, void **); uint32_t, void **); extern int qla24xx_dump_ram(struct qla_hw_data *, uint32_t, uint32_t *, extern int qla24xx_dump_ram(struct qla_hw_data *, uint32_t, uint32_t *, uint32_t, void **); uint32_t, void **); extern void qla24xx_pause_risc(struct device_reg_24xx __iomem *); extern void qla24xx_pause_risc(struct device_reg_24xx __iomem *, struct qla_hw_data *); extern int qla24xx_soft_reset(struct qla_hw_data *); extern int qla24xx_soft_reset(struct qla_hw_data *); drivers/scsi/qla2xxx/qla_def.h +7 −0 Original line number Original line Diff line number Diff line Loading @@ -3147,6 +3147,13 @@ struct qla_hw_data { struct qla2xxx_fw_dump *fw_dump; struct qla2xxx_fw_dump *fw_dump; uint32_t fw_dump_len; uint32_t fw_dump_len; int fw_dumped; int fw_dumped; unsigned long fw_dump_cap_flags; #define RISC_PAUSE_CMPL 0 #define DMA_SHUTDOWN_CMPL 1 #define ISP_RESET_CMPL 2 #define RISC_RDY_AFT_RESET 3 #define RISC_SRAM_DUMP_CMPL 4 #define RISC_EXT_MEM_DUMP_CMPL 5 int fw_dump_reading; int fw_dump_reading; int prev_minidump_failed; int prev_minidump_failed; dma_addr_t eft_dma; dma_addr_t eft_dma; Loading drivers/scsi/qla2xxx/qla_init.c +1 −0 Original line number Original line Diff line number Diff line Loading @@ -1476,6 +1476,7 @@ qla2x00_alloc_fw_dump(scsi_qla_host_t *vha) } } ha->fw_dumped = 0; ha->fw_dumped = 0; ha->fw_dump_cap_flags = 0; dump_size = fixed_size = mem_size = eft_size = fce_size = mq_size = 0; dump_size = fixed_size = mem_size = eft_size = fce_size = mq_size = 0; req_q_size = rsp_q_size = 0; req_q_size = rsp_q_size = 0; Loading drivers/scsi/qla2xxx/qla_os.c +1 −0 Original line number Original line Diff line number Diff line Loading @@ -3654,6 +3654,7 @@ qla2x00_free_fw_dump(struct qla_hw_data *ha) ha->eft = NULL; ha->eft = NULL; ha->eft_dma = 0; ha->eft_dma = 0; ha->fw_dumped = 0; ha->fw_dumped = 0; ha->fw_dump_cap_flags = 0; ha->fw_dump_reading = 0; ha->fw_dump_reading = 0; ha->fw_dump = NULL; ha->fw_dump = NULL; ha->fw_dump_len = 0; ha->fw_dump_len = 0; Loading Loading
drivers/scsi/qla2xxx/qla_dbg.c +32 −10 Original line number Original line Diff line number Diff line Loading @@ -277,9 +277,15 @@ qla24xx_dump_memory(struct qla_hw_data *ha, uint32_t *code_ram, if (rval != QLA_SUCCESS) if (rval != QLA_SUCCESS) return rval; return rval; set_bit(RISC_SRAM_DUMP_CMPL, &ha->fw_dump_cap_flags); /* External Memory. */ /* External Memory. */ return qla24xx_dump_ram(ha, 0x100000, *nxt, rval = qla24xx_dump_ram(ha, 0x100000, *nxt, ha->fw_memory_size - 0x100000 + 1, nxt); ha->fw_memory_size - 0x100000 + 1, nxt); if (rval == QLA_SUCCESS) set_bit(RISC_EXT_MEM_DUMP_CMPL, &ha->fw_dump_cap_flags); return rval; } } static uint32_t * static uint32_t * Loading @@ -297,12 +303,14 @@ qla24xx_read_window(struct device_reg_24xx __iomem *reg, uint32_t iobase, } } void void qla24xx_pause_risc(struct device_reg_24xx __iomem *reg) qla24xx_pause_risc(struct device_reg_24xx __iomem *reg, struct qla_hw_data *ha) { { WRT_REG_DWORD(®->hccr, HCCRX_SET_RISC_PAUSE); WRT_REG_DWORD(®->hccr, HCCRX_SET_RISC_PAUSE); /* 100 usec delay is sufficient enough for hardware to pause RISC */ /* 100 usec delay is sufficient enough for hardware to pause RISC */ udelay(100); udelay(100); if (RD_REG_DWORD(®->host_status) & HSRX_RISC_PAUSED) set_bit(RISC_PAUSE_CMPL, &ha->fw_dump_cap_flags); } } int int Loading @@ -325,6 +333,8 @@ qla24xx_soft_reset(struct qla_hw_data *ha) udelay(10); udelay(10); } } if (!(RD_REG_DWORD(®->ctrl_status) & CSRX_DMA_ACTIVE)) set_bit(DMA_SHUTDOWN_CMPL, &ha->fw_dump_cap_flags); WRT_REG_DWORD(®->ctrl_status, WRT_REG_DWORD(®->ctrl_status, CSRX_ISP_SOFT_RESET|CSRX_DMA_SHUTDOWN|MWB_4096_BYTES); CSRX_ISP_SOFT_RESET|CSRX_DMA_SHUTDOWN|MWB_4096_BYTES); Loading @@ -340,6 +350,9 @@ qla24xx_soft_reset(struct qla_hw_data *ha) udelay(10); udelay(10); } } if (!(RD_REG_DWORD(®->ctrl_status) & CSRX_ISP_SOFT_RESET)) set_bit(ISP_RESET_CMPL, &ha->fw_dump_cap_flags); WRT_REG_DWORD(®->hccr, HCCRX_CLR_RISC_RESET); WRT_REG_DWORD(®->hccr, HCCRX_CLR_RISC_RESET); RD_REG_DWORD(®->hccr); /* PCI Posting. */ RD_REG_DWORD(®->hccr); /* PCI Posting. */ Loading @@ -350,6 +363,8 @@ qla24xx_soft_reset(struct qla_hw_data *ha) else else rval = QLA_FUNCTION_TIMEOUT; rval = QLA_FUNCTION_TIMEOUT; } } if (rval == QLA_SUCCESS) set_bit(RISC_RDY_AFT_RESET, &ha->fw_dump_cap_flags); return rval; return rval; } } Loading Loading @@ -646,12 +661,13 @@ qla2xxx_dump_post_process(scsi_qla_host_t *vha, int rval) if (rval != QLA_SUCCESS) { if (rval != QLA_SUCCESS) { ql_log(ql_log_warn, vha, 0xd000, ql_log(ql_log_warn, vha, 0xd000, "Failed to dump firmware (%x).\n", rval); "Failed to dump firmware (%x), dump status flags (0x%lx).\n", rval, ha->fw_dump_cap_flags); ha->fw_dumped = 0; ha->fw_dumped = 0; } else { } else { ql_log(ql_log_info, vha, 0xd001, ql_log(ql_log_info, vha, 0xd001, "Firmware dump saved to temp buffer (%ld/%p).\n", "Firmware dump saved to temp buffer (%ld/%p), dump status flags (0x%lx).\n", vha->host_no, ha->fw_dump); vha->host_no, ha->fw_dump, ha->fw_dump_cap_flags); ha->fw_dumped = 1; ha->fw_dumped = 1; qla2x00_post_uevent_work(vha, QLA_UEVENT_CODE_FW_DUMP); qla2x00_post_uevent_work(vha, QLA_UEVENT_CODE_FW_DUMP); } } Loading Loading @@ -1040,6 +1056,7 @@ qla24xx_fw_dump(scsi_qla_host_t *vha, int hardware_locked) risc_address = ext_mem_cnt = 0; risc_address = ext_mem_cnt = 0; flags = 0; flags = 0; ha->fw_dump_cap_flags = 0; if (!hardware_locked) if (!hardware_locked) spin_lock_irqsave(&ha->hardware_lock, flags); spin_lock_irqsave(&ha->hardware_lock, flags); Loading @@ -1066,7 +1083,7 @@ qla24xx_fw_dump(scsi_qla_host_t *vha, int hardware_locked) * Pause RISC. No need to track timeout, as resetting the chip * Pause RISC. No need to track timeout, as resetting the chip * is the right approach incase of pause timeout * is the right approach incase of pause timeout */ */ qla24xx_pause_risc(reg); qla24xx_pause_risc(reg, ha); /* Host interface registers. */ /* Host interface registers. */ dmp_reg = ®->flash_addr; dmp_reg = ®->flash_addr; Loading Loading @@ -1290,6 +1307,7 @@ qla25xx_fw_dump(scsi_qla_host_t *vha, int hardware_locked) risc_address = ext_mem_cnt = 0; risc_address = ext_mem_cnt = 0; flags = 0; flags = 0; ha->fw_dump_cap_flags = 0; if (!hardware_locked) if (!hardware_locked) spin_lock_irqsave(&ha->hardware_lock, flags); spin_lock_irqsave(&ha->hardware_lock, flags); Loading Loading @@ -1317,7 +1335,7 @@ qla25xx_fw_dump(scsi_qla_host_t *vha, int hardware_locked) * Pause RISC. No need to track timeout, as resetting the chip * Pause RISC. No need to track timeout, as resetting the chip * is the right approach incase of pause timeout * is the right approach incase of pause timeout */ */ qla24xx_pause_risc(reg); qla24xx_pause_risc(reg, ha); /* Host/Risc registers. */ /* Host/Risc registers. */ iter_reg = fw->host_risc_reg; iter_reg = fw->host_risc_reg; Loading Loading @@ -1608,6 +1626,7 @@ qla81xx_fw_dump(scsi_qla_host_t *vha, int hardware_locked) risc_address = ext_mem_cnt = 0; risc_address = ext_mem_cnt = 0; flags = 0; flags = 0; ha->fw_dump_cap_flags = 0; if (!hardware_locked) if (!hardware_locked) spin_lock_irqsave(&ha->hardware_lock, flags); spin_lock_irqsave(&ha->hardware_lock, flags); Loading @@ -1634,7 +1653,7 @@ qla81xx_fw_dump(scsi_qla_host_t *vha, int hardware_locked) * Pause RISC. No need to track timeout, as resetting the chip * Pause RISC. No need to track timeout, as resetting the chip * is the right approach incase of pause timeout * is the right approach incase of pause timeout */ */ qla24xx_pause_risc(reg); qla24xx_pause_risc(reg, ha); /* Host/Risc registers. */ /* Host/Risc registers. */ iter_reg = fw->host_risc_reg; iter_reg = fw->host_risc_reg; Loading Loading @@ -1928,6 +1947,7 @@ qla83xx_fw_dump(scsi_qla_host_t *vha, int hardware_locked) risc_address = ext_mem_cnt = 0; risc_address = ext_mem_cnt = 0; flags = 0; flags = 0; ha->fw_dump_cap_flags = 0; if (!hardware_locked) if (!hardware_locked) spin_lock_irqsave(&ha->hardware_lock, flags); spin_lock_irqsave(&ha->hardware_lock, flags); Loading @@ -1953,7 +1973,7 @@ qla83xx_fw_dump(scsi_qla_host_t *vha, int hardware_locked) * Pause RISC. No need to track timeout, as resetting the chip * Pause RISC. No need to track timeout, as resetting the chip * is the right approach incase of pause timeout * is the right approach incase of pause timeout */ */ qla24xx_pause_risc(reg); qla24xx_pause_risc(reg, ha); WRT_REG_DWORD(®->iobase_addr, 0x6000); WRT_REG_DWORD(®->iobase_addr, 0x6000); dmp_reg = ®->iobase_window; dmp_reg = ®->iobase_window; Loading Loading @@ -2376,10 +2396,12 @@ qla83xx_fw_dump(scsi_qla_host_t *vha, int hardware_locked) nxt += sizeof(fw->code_ram); nxt += sizeof(fw->code_ram); nxt += (ha->fw_memory_size - 0x100000 + 1); nxt += (ha->fw_memory_size - 0x100000 + 1); goto copy_queue; goto copy_queue; } else } else { set_bit(RISC_RDY_AFT_RESET, &ha->fw_dump_cap_flags); ql_log(ql_log_warn, vha, 0xd010, ql_log(ql_log_warn, vha, 0xd010, "bigger hammer success?\n"); "bigger hammer success?\n"); } } } rval = qla24xx_dump_memory(ha, fw->code_ram, sizeof(fw->code_ram), rval = qla24xx_dump_memory(ha, fw->code_ram, sizeof(fw->code_ram), &nxt); &nxt); Loading
drivers/scsi/qla2xxx/qla_dbg.h +2 −1 Original line number Original line Diff line number Diff line Loading @@ -353,5 +353,6 @@ extern int qla27xx_dump_mpi_ram(struct qla_hw_data *, uint32_t, uint32_t *, uint32_t, void **); uint32_t, void **); extern int qla24xx_dump_ram(struct qla_hw_data *, uint32_t, uint32_t *, extern int qla24xx_dump_ram(struct qla_hw_data *, uint32_t, uint32_t *, uint32_t, void **); uint32_t, void **); extern void qla24xx_pause_risc(struct device_reg_24xx __iomem *); extern void qla24xx_pause_risc(struct device_reg_24xx __iomem *, struct qla_hw_data *); extern int qla24xx_soft_reset(struct qla_hw_data *); extern int qla24xx_soft_reset(struct qla_hw_data *);
drivers/scsi/qla2xxx/qla_def.h +7 −0 Original line number Original line Diff line number Diff line Loading @@ -3147,6 +3147,13 @@ struct qla_hw_data { struct qla2xxx_fw_dump *fw_dump; struct qla2xxx_fw_dump *fw_dump; uint32_t fw_dump_len; uint32_t fw_dump_len; int fw_dumped; int fw_dumped; unsigned long fw_dump_cap_flags; #define RISC_PAUSE_CMPL 0 #define DMA_SHUTDOWN_CMPL 1 #define ISP_RESET_CMPL 2 #define RISC_RDY_AFT_RESET 3 #define RISC_SRAM_DUMP_CMPL 4 #define RISC_EXT_MEM_DUMP_CMPL 5 int fw_dump_reading; int fw_dump_reading; int prev_minidump_failed; int prev_minidump_failed; dma_addr_t eft_dma; dma_addr_t eft_dma; Loading
drivers/scsi/qla2xxx/qla_init.c +1 −0 Original line number Original line Diff line number Diff line Loading @@ -1476,6 +1476,7 @@ qla2x00_alloc_fw_dump(scsi_qla_host_t *vha) } } ha->fw_dumped = 0; ha->fw_dumped = 0; ha->fw_dump_cap_flags = 0; dump_size = fixed_size = mem_size = eft_size = fce_size = mq_size = 0; dump_size = fixed_size = mem_size = eft_size = fce_size = mq_size = 0; req_q_size = rsp_q_size = 0; req_q_size = rsp_q_size = 0; Loading
drivers/scsi/qla2xxx/qla_os.c +1 −0 Original line number Original line Diff line number Diff line Loading @@ -3654,6 +3654,7 @@ qla2x00_free_fw_dump(struct qla_hw_data *ha) ha->eft = NULL; ha->eft = NULL; ha->eft_dma = 0; ha->eft_dma = 0; ha->fw_dumped = 0; ha->fw_dumped = 0; ha->fw_dump_cap_flags = 0; ha->fw_dump_reading = 0; ha->fw_dump_reading = 0; ha->fw_dump = NULL; ha->fw_dump = NULL; ha->fw_dump_len = 0; ha->fw_dump_len = 0; Loading