Commit 638f7977 authored by Arnd Bergmann's avatar Arnd Bergmann
Browse files

Merge tag 'zynqmp-dt-for-v5.12' of https://github.com/Xilinx/linux-xlnx into arm/dt 

arm64: dts: ZynqMP DT changes for v5.12

- Wire clock chips present on boards
- Enable reset, qspi, nand, watchdog and DP IPs
- Enable phy driver for sata and DP
- Add iommu description
- Add support for zcu104 revC+ boards

- Various small changes
  - Add missing labels
  - Fix typos in documentation
  - Add missing boards

* tag 'zynqmp-dt-for-v5.12' of https://github.com/Xilinx/linux-xlnx:
  arm64: dts: zynqmp: Wire up the DisplayPort subsystem
  arm64: dts: zynqmp: Add DisplayPort subsystem
  arm64: dts: zynqmp: Add DPDMA node
  dt-bindings: arm: Fix typo in zcu111 board
  arm64: dts: zynqmp: Add description for zcu104 revC
  arm64: dts: zynqmp: Add missing iommu IDs
  arm64: dts: zynqmp: Add missing lpd watchdog node
  arm64: dts: zynqmp: Wire zynqmp qspi controller
  arm64: dts: zynqmp: Wire arasan nand controller
  arm64: dts: zynqmp: Add missing mio-bank properties to sdhcis
  arm64: dts: zynqmp: Add label for zynqmp_ipi
  arm64: dts: zynqmp: Enable phy driver for Sata on zcu102/zcu104/zcu106
  arm64: dts: zynqmp: Enable reset controller driver
  arm64: dts: zynqmp: Enable si5341 driver for zcu102/106/111
  arm64: dts: zynqmp: Add DT description for si5328 for zcu102/zcu106
  arm64: dts: zynqmp: Fix u48 si5382 chip on zcu111
  arm64: dts: zynqmp: Add address-cells property to interrupt controllers

Link: https://lore.kernel.org/r/b1a6f89e-f6b4-757b-daf0-d2f1844b833d@xilinx.com


Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parents f3d8876a 55563399

Documentation/devicetree/bindings/arm/xilinx.yaml

+2 −1
Original line number Diff line number Diff line
@@ -91,6 +91,7 @@ properties: 
        items:

          - enum:

              - xlnx,zynqmp-zcu104-revA

              - xlnx,zynqmp-zcu104-revC

              - xlnx,zynqmp-zcu104-rev1.0

          - const: xlnx,zynqmp-zcu104

          - const: xlnx,zynqmp
@@ -107,7 +108,7 @@ properties: 
        items:

          - enum:

              - xlnx,zynqmp-zcu111-revA

              - xlnx,zynqmp-zcu11-rev1.0

              - xlnx,zynqmp-zcu111-rev1.0

          - const: xlnx,zynqmp-zcu111

          - const: xlnx,zynqmp

arch/arm64/boot/dts/xilinx/Makefile

+1 −0
Original line number Diff line number Diff line
@@ -13,5 +13,6 @@ dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu102-revA.dtb 
dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu102-revB.dtb

dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu102-rev1.0.dtb

dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu104-revA.dtb

dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu104-revC.dtb

dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu106-revA.dtb

dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu111-revA.dtb

arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi

+22 −0
Original line number Diff line number Diff line
@@ -116,6 +116,10 @@ &lpd_dma_chan8 { 
	clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;

};



&nand0 {

	clocks = <&zynqmp_clk NAND_REF>, <&zynqmp_clk LPD_LSBUS>;

};



&gem0 {

	clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM0_REF>,

		 <&zynqmp_clk GEM0_TX>, <&zynqmp_clk GEM0_RX>,
@@ -160,6 +164,10 @@ &pcie { 
	clocks = <&zynqmp_clk PCIE_REF>;

};



&qspi {

	clocks = <&zynqmp_clk QSPI_REF>, <&zynqmp_clk LPD_LSBUS>;

};



&sata {

	clocks = <&zynqmp_clk SATA_REF>;

};
@@ -215,3 +223,17 @@ &usb1 { 
&watchdog0 {

	clocks = <&zynqmp_clk WDT>;

};



&lpd_watchdog {

	clocks = <&zynqmp_clk LPD_WDT>;

};



&zynqmp_dpdma {

	clocks = <&zynqmp_clk DPDMA_REF>;

};



&zynqmp_dpsub {

	clocks = <&zynqmp_clk TOPSW_LSBUS>,

		 <&zynqmp_clk DP_AUDIO_REF>,

		 <&zynqmp_clk DP_VIDEO_REF>;

};

arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts

+33 −0
Original line number Diff line number Diff line
@@ -15,6 +15,7 @@ 
#include <dt-bindings/input/input.h>

#include <dt-bindings/interrupt-controller/irq.h>

#include <dt-bindings/gpio/gpio.h>

#include <dt-bindings/phy/phy.h>



/ {

	model = "ZynqMP ZCU100 RevC";
@@ -108,6 +109,18 @@ ina226 { 
		compatible = "iio-hwmon";

		io-channels = <&u35 0>, <&u35 1>, <&u35 2>, <&u35 3>;

	};



	si5335a_0: clk26 {

		compatible = "fixed-clock";

		#clock-cells = <0>;

		clock-frequency = <26000000>;

	};



	si5335a_1: clk27 {

		compatible = "fixed-clock";

		#clock-cells = <0>;

		clock-frequency = <27000000>;

	};

};



&dcc {
@@ -224,6 +237,13 @@ i2csw_7: i2c@7 { 
	};

};



&psgtr {

	status = "okay";

	/* usb3, dps */

	clocks = <&si5335a_0>, <&si5335a_1>;

	clock-names = "ref0", "ref1";

};



&rtc {

	status = "okay";

};
@@ -233,11 +253,13 @@ &sdhci0 { 
	status = "okay";

	no-1-8-v;

	disable-wp;

	xlnx,mio-bank = <0>;

};



&sdhci1 {

	status = "okay";

	bus-width = <0x4>;

	xlnx,mio-bank = <0>;

	non-removable;

	disable-wp;

	cap-power-off-card;
@@ -293,3 +315,14 @@ &usb1 { 
&watchdog0 {

	status = "okay";

};



&zynqmp_dpdma {

	status = "okay";

};



&zynqmp_dpsub {

	status = "okay";

	phy-names = "dp-phy0", "dp-phy1";

	phys = <&psgtr 1 PHY_TYPE_DP 0 1>,

	       <&psgtr 0 PHY_TYPE_DP 1 1>;

};

arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts

+93 −1
Original line number Diff line number Diff line
@@ -13,6 +13,7 @@ 
#include "zynqmp-clk-ccf.dtsi"

#include <dt-bindings/input/input.h>

#include <dt-bindings/gpio/gpio.h>

#include <dt-bindings/phy/phy.h>



/ {

	model = "ZynqMP ZCU102 RevA";
@@ -132,6 +133,19 @@ ina226-u75 { 
		compatible = "iio-hwmon";

		io-channels = <&u75 0>, <&u75 1>, <&u75 2>, <&u75 3>;

	};



	/* 48MHz reference crystal */

	ref48: ref48M {

		compatible = "fixed-clock";

		#clock-cells = <0>;

		clock-frequency = <48000000>;

	};



	refhdmi: refhdmi {

		compatible = "fixed-clock";

		#clock-cells = <0>;

		clock-frequency = <114285000>;

	};

};



&can1 {
@@ -483,9 +497,56 @@ i2c@1 { 
			#size-cells = <0>;

			reg = <1>;

			si5341: clock-generator@36 { /* SI5341 - u69 */

				compatible = "silabs,si5341";

				reg = <0x36>;

			};

				#clock-cells = <2>;

				#address-cells = <1>;

				#size-cells = <0>;

				clocks = <&ref48>;

				clock-names = "xtal";

				clock-output-names = "si5341";



				si5341_0: out@0 {

					/* refclk0 for PS-GT, used for DP */

					reg = <0>;

					always-on;

				};

				si5341_2: out@2 {

					/* refclk2 for PS-GT, used for USB3 */

					reg = <2>;

					always-on;

				};

				si5341_3: out@3 {

					/* refclk3 for PS-GT, used for SATA */

					reg = <3>;

					always-on;

				};

				si5341_4: out@4 {

					/* refclk4 for PS-GT, used for PCIE slot */

					reg = <4>;

					always-on;

				};

				si5341_5: out@5 {

					/* refclk5 for PS-GT, used for PCIE */

					reg = <5>;

					always-on;

				};

				si5341_6: out@6 {

					/* refclk6 PL CLK125 */

					reg = <6>;

					always-on;

				};

				si5341_7: out@7 {

					/* refclk7 PL CLK74 */

					reg = <7>;

					always-on;

				};

				si5341_9: out@9 {

					/* refclk9 used for PS_REF_CLK 33.3 MHz */

					reg = <9>;

					always-on;

				};

			};

		};

		i2c@2 {

			#address-cells = <1>;
@@ -526,6 +587,17 @@ si5328: clock-generator@69 {/* SI5328 - u20 */ 
				 * interrupt-parent = <&>;

				 * interrupts = <>;

				 */

				#address-cells = <1>;

				#size-cells = <0>;

				#clock-cells = <1>;

				clocks = <&refhdmi>;

				clock-names = "xtal";

				clock-output-names = "si5328";



				si5328_clk: clk0@0 {

					reg = <0>;

					clock-frequency = <27000000>;

				};

			};

		};

		/* 5 - 7 unconnected */
@@ -592,6 +664,13 @@ &pcie { 
	status = "okay";

};



&psgtr {

	status = "okay";

	/* pcie, sata, usb3, dp */

	clocks = <&si5341 0 5>, <&si5341 0 3>, <&si5341 0 2>, <&si5341 0 0>;

	clock-names = "ref0", "ref1", "ref2", "ref3";

};



&rtc {

	status = "okay";

};
@@ -607,12 +686,15 @@ &sata { 
	ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;

	ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;

	ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;

	phy-names = "sata-phy";

	phys = <&psgtr 3 PHY_TYPE_SATA 1 1>;

};



/* SD1 with level shifter */

&sdhci1 {

	status = "okay";

	no-1-8-v;

	xlnx,mio-bank = <1>;

};



&uart0 {
@@ -632,3 +714,13 @@ &usb0 { 
&watchdog0 {

	status = "okay";

};



&zynqmp_dpdma {

	status = "okay";

};



&zynqmp_dpsub {

	status = "okay";

	phy-names = "dp-phy0";

	phys = <&psgtr 1 PHY_TYPE_DP 0 3>;

};