Commit 63f4e4b4 authored by Konrad Dybcio's avatar Konrad Dybcio Committed by Bjorn Andersson
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arm64: dts: qcom: msm8998: Use the correct GPLL0_DIV leg for MMCC 



MMCC has its own GPLL0 legs - one for 1-1 and one for div-2 output.
We've already been using the correct one in the non-div case, start
doing so for the other one as well.

Reviewed-by: default avatarJeffrey Hugo <quic_jhugo@quicinc.com>
Signed-off-by: default avatarKonrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20230622-topic-8998clk-v2-8-6222fbc2916b@linaro.org


Signed-off-by: default avatarBjorn Andersson <andersson@kernel.org>
parent 00ada6af

arch/arm64/boot/dts/qcom/msm8998.dtsi

+4 −2
Original line number Diff line number Diff line
@@ -2724,7 +2724,8 @@ mmcc: clock-controller@c8c0000 { 
				      "dsi1byte",

				      "hdmipll",

				      "dplink",

				      "dpvco";

				      "dpvco",

				      "gpll0_div";

			clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,

				 <&gcc GCC_MMSS_GPLL0_CLK>,

				 <0>,
@@ -2733,7 +2734,8 @@ mmcc: clock-controller@c8c0000 { 
				 <0>,

				 <0>,

				 <0>,

				 <0>;

				 <0>,

				 <&gcc GCC_MMSS_GPLL0_DIV_CLK>;

		};



		mmss_smmu: iommu@cd00000 {