Commit 63fb606a authored Oct 04, 2022 by Dinh Nguyen

arm: dts: socfpga: remove "clk-phase" in sdmmc_clk



Now that the SDMMC driver can use the "clk-phase-sd-hs" binding, we don't
need the clk-phase in the sdmmc_clk anymore.

Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>

parent 2dbf5494

arch/arm/boot/dts/socfpga.dtsi

+0 −1

Original line number	Diff line number	Diff line
		@@ -453,7 +453,6 @@ sdmmc_clk: sdmmc_clk {
		compatible = "altr,socfpga-gate-clk";
		clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>;
		clk-gate = <0xa0 8>;
		clk-phase = <0 135>;
		};

		sdmmc_clk_divided: sdmmc_clk_divided {

arch/arm/boot/dts/socfpga_arria10.dtsi

+0 −1

Original line number	Diff line number	Diff line
		@@ -365,7 +365,6 @@ sdmmc_clk: sdmmc_clk {
		compatible = "altr,socfpga-a10-gate-clk";
		clocks = <&sdmmc_free_clk>;
		clk-gate = <0xC8 5>;
		clk-phase = <0 135>;
		};

		qspi_clk: qspi_clk {