Commit 64200c46 authored by Mauro Rossi's avatar Mauro Rossi Committed by Alex Deucher
Browse files

drm/amdgpu: enable DC support for SI parts (v2) 



[Why]
amdgpu_device.c requires changes for SI chipsets support
si.c require changes for Display Manager IP block enabling

[How]
amdgpu_device.c: add SI families in amdgpu_device_asic_has_dc_support()
si.c: changes in si_set_ip_blocks() for Display Manager IP blocks enablement

(v1) NOTE: As per Kaveri and older amdgpu.dc=1 kernel cmdline is required

(v2) fix for bc011f9350 ("drm/amdgpu: Change SI/CI gfx/sdma/smu init sequence")
     remove CHIP_HAINAN support since it does not have physical DCE6 module

Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarMauro Rossi <issor.oruam@gmail.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent f784112f

drivers/gpu/drm/amd/amdgpu/amdgpu_device.c

+6 −0
Original line number Diff line number Diff line
@@ -2775,6 +2775,12 @@ bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type) 
{

	switch (asic_type) {

#if defined(CONFIG_DRM_AMD_DC)

#if defined(CONFIG_DRM_AMD_DC_SI)

	case CHIP_TAHITI:

	case CHIP_PITCAIRN:

	case CHIP_VERDE:

	case CHIP_OLAND:

#endif

	case CHIP_BONAIRE:

	case CHIP_KAVERI:

	case CHIP_KABINI:

drivers/gpu/drm/amd/amdgpu/si.c

+10 −0
Original line number Diff line number Diff line
@@ -52,6 +52,8 @@ 
#include "bif/bif_3_0_d.h"

#include "bif/bif_3_0_sh_mask.h"



#include "amdgpu_dm.h"



static const u32 tahiti_golden_registers[] =

{

	mmAZALIA_SCLK_CONTROL, 0x00000030, 0x00000011,
@@ -2546,6 +2548,10 @@ int si_set_ip_blocks(struct amdgpu_device *adev) 
		amdgpu_device_ip_block_add(adev, &si_smu_ip_block);

		if (adev->enable_virtual_display)

			amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);

#if defined(CONFIG_DRM_AMD_DC) && defined(CONFIG_DRM_AMD_DC_SI)

		else if (amdgpu_device_has_dc_support(adev))

			amdgpu_device_ip_block_add(adev, &dm_ip_block);

#endif

		else

			amdgpu_device_ip_block_add(adev, &dce_v6_0_ip_block);

		amdgpu_device_ip_block_add(adev, &uvd_v3_1_ip_block);
@@ -2560,6 +2566,10 @@ int si_set_ip_blocks(struct amdgpu_device *adev) 
		amdgpu_device_ip_block_add(adev, &si_smu_ip_block);

		if (adev->enable_virtual_display)

			amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);

#if defined(CONFIG_DRM_AMD_DC) && defined(CONFIG_DRM_AMD_DC_SI)

		else if (amdgpu_device_has_dc_support(adev))

			amdgpu_device_ip_block_add(adev, &dm_ip_block);

#endif

		else

			amdgpu_device_ip_block_add(adev, &dce_v6_4_ip_block);

		amdgpu_device_ip_block_add(adev, &uvd_v3_1_ip_block);