Commit 65781c78 authored by Monk Liu's avatar Monk Liu Committed by Alex Deucher
Browse files

drm/amdgpu/SRIOV:implement guilty job TDR for(V2) 



1,TDR will kickout guilty job if it hang exceed the threshold
of the given one from kernel paramter "job_hang_limit", that
way a bad command stream will not infinitly cause GPU hang.

by default this threshold is 1 so a job will be kicked out
after it hang.

2,if a job timeout TDR routine will not reset all sched/ring,
instead if will only reset on the givn one which is indicated
by @job of amdgpu_sriov_gpu_reset, that way we don't need to
reset and recover each sched/ring if we already know which job
cause GPU hang.

3,unblock sriov_gpu_reset for AI family.

V2:
1:put kickout guilty job after sched parked.
2:since parking scheduler prior to kickout already occupies a
while, we can do last check on the in question job before
doing hw_reset.

TODO:
1:when a job is considered as guilty, we should mark some flag
in its fence status flag, and let UMD side aware that this
fence signaling is not due to job complete but job hang.

2:if gpu reset cause all video memory lost, we need introduce
a new policy to implement TDR, like drop all jobs not yet
signaled, and all IOCTL on this device will return ERROR
DEVICE_LOST.
this will be implemented later.

Signed-off-by: default avatarMonk Liu <Monk.Liu@amd.com>
Reviewed-by: default avatarChristian König <christian.koenig@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 75fbed20

drivers/gpu/drm/amd/amdgpu/amdgpu.h

+1 −0
Original line number Diff line number Diff line
@@ -109,6 +109,7 @@ extern int amdgpu_prim_buf_per_se; 
extern int amdgpu_pos_buf_per_se;

extern int amdgpu_cntl_sb_buf_per_se;

extern int amdgpu_param_buf_per_se;

extern int amdgpu_job_hang_limit;



#define AMDGPU_DEFAULT_GTT_SIZE_MB		3072ULL /* 3GB by default */

#define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS	        3000

drivers/gpu/drm/amd/amdgpu/amdgpu_device.c

+34 −9
Original line number Diff line number Diff line
@@ -2617,7 +2617,7 @@ static int amdgpu_recover_vram_from_shadow(struct amdgpu_device *adev, 
 */

int amdgpu_sriov_gpu_reset(struct amdgpu_device *adev, struct amdgpu_job *job)

{

	int i, r = 0;

	int i, j, r = 0;

	int resched;

	struct amdgpu_bo *bo, *tmp;

	struct amdgpu_ring *ring;
@@ -2630,19 +2630,36 @@ int amdgpu_sriov_gpu_reset(struct amdgpu_device *adev, struct amdgpu_job *job) 
	/* block TTM */

	resched = ttm_bo_lock_delayed_workqueue(&adev->mman.bdev);



	/* block scheduler */

	for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {

		ring = adev->rings[i];

	/* we start from the ring trigger GPU hang */

	j = job ? job->ring->idx : 0;



	/* block scheduler */

	for (i = j; i < j + AMDGPU_MAX_RINGS; ++i) {

		ring = adev->rings[i % AMDGPU_MAX_RINGS];

		if (!ring || !ring->sched.thread)

			continue;



		kthread_park(ring->sched.thread);

		amd_sched_hw_job_reset(&ring->sched);



		if (job && j != i)

			continue;



		/* here give the last chance to check if fence signaled

		 * since we already pay some time on kthread_park */

		if (job && dma_fence_is_signaled(&job->base.s_fence->finished)) {

			kthread_unpark(ring->sched.thread);

			goto give_up_reset;

		}



		if (amd_sched_invalidate_job(&job->base, amdgpu_job_hang_limit))

			amd_sched_job_kickout(&job->base);



		/* only do job_reset on the hang ring if @job not NULL */

		amd_sched_hw_job_reset(&ring->sched);



		/* after all hw jobs are reset, hw fence is meaningless, so force_completion */

	amdgpu_fence_driver_force_completion(adev);

		amdgpu_fence_driver_force_completion_ring(ring);

	}



	/* request to take full control of GPU before re-initialization  */

	if (job)
@@ -2695,20 +2712,28 @@ int amdgpu_sriov_gpu_reset(struct amdgpu_device *adev, struct amdgpu_job *job) 
	}

	dma_fence_put(fence);



	for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {

		struct amdgpu_ring *ring = adev->rings[i];

	for (i = j; i < j + AMDGPU_MAX_RINGS; ++i) {

		ring = adev->rings[i % AMDGPU_MAX_RINGS];

		if (!ring || !ring->sched.thread)

			continue;



		if (job && j != i) {

			kthread_unpark(ring->sched.thread);

			continue;

		}



		amd_sched_job_recovery(&ring->sched);

		kthread_unpark(ring->sched.thread);

	}



	drm_helper_resume_force_mode(adev->ddev);

give_up_reset:

	ttm_bo_unlock_delayed_workqueue(&adev->mman.bdev, resched);

	if (r) {

		/* bad news, how to tell it to userspace ? */

		dev_info(adev->dev, "GPU reset failed\n");

	} else {

		dev_info(adev->dev, "GPU reset successed!\n");

	}



	adev->gfx.in_reset = false;

drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c

+4 −0
Original line number Diff line number Diff line
@@ -111,6 +111,7 @@ int amdgpu_prim_buf_per_se = 0; 
int amdgpu_pos_buf_per_se = 0;

int amdgpu_cntl_sb_buf_per_se = 0;

int amdgpu_param_buf_per_se = 0;

int amdgpu_job_hang_limit = 0;



MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes");

module_param_named(vramlimit, amdgpu_vram_limit, int, 0600);
@@ -233,6 +234,9 @@ module_param_named(cntl_sb_buf_per_se, amdgpu_cntl_sb_buf_per_se, int, 0444); 
MODULE_PARM_DESC(param_buf_per_se, "the size of Off-Chip Pramater Cache per Shader Engine (default depending on gfx)");

module_param_named(param_buf_per_se, amdgpu_param_buf_per_se, int, 0444);



MODULE_PARM_DESC(job_hang_limit, "how much time allow a job hang and not drop it (default 0)");

module_param_named(job_hang_limit, amdgpu_job_hang_limit, int ,0444);





static const struct pci_device_id pciidlist[] = {

#ifdef  CONFIG_DRM_AMDGPU_SI

drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c

+6 −0
Original line number Diff line number Diff line
@@ -541,6 +541,12 @@ void amdgpu_fence_driver_force_completion(struct amdgpu_device *adev) 
	}

}



void amdgpu_fence_driver_force_completion_ring(struct amdgpu_ring *ring)

{

	if (ring)

		amdgpu_fence_write(ring, ring->fence_drv.sync_seq);

}



/*

 * Common fence implementation

 */

drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h

+1 −0
Original line number Diff line number Diff line
@@ -76,6 +76,7 @@ struct amdgpu_fence_driver { 
int amdgpu_fence_driver_init(struct amdgpu_device *adev);

void amdgpu_fence_driver_fini(struct amdgpu_device *adev);

void amdgpu_fence_driver_force_completion(struct amdgpu_device *adev);

void amdgpu_fence_driver_force_completion_ring(struct amdgpu_ring *ring);



int amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring,

				  unsigned num_hw_submission);