Commit 65ba96e9 authored by Hawking Zhang's avatar Hawking Zhang Committed by Alex Deucher
Browse files

drm/amdgpu: Move to common indirect reg access helper 



Replace soc15, nv, soc21 specific callbacks with common
one. so we don't need to duplicate code when introduce
new asics.

Signed-off-by: default avatarHawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: default avatarLikun Gao <Likun.Gao@amd.com>
Acked-by: default avatarChristian König <christian.koenig@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 37080887

drivers/gpu/drm/amd/amdgpu/amdgpu.h

+0 −4
Original line number Diff line number Diff line
@@ -1111,16 +1111,12 @@ void amdgpu_mm_wreg8(struct amdgpu_device *adev, uint32_t offset, uint8_t value) 
uint8_t amdgpu_mm_rreg8(struct amdgpu_device *adev, uint32_t offset);



u32 amdgpu_device_indirect_rreg(struct amdgpu_device *adev,

				u32 pcie_index, u32 pcie_data,

				u32 reg_addr);

u64 amdgpu_device_indirect_rreg64(struct amdgpu_device *adev,

				  u32 pcie_index, u32 pcie_data,

				  u32 reg_addr);

void amdgpu_device_indirect_wreg(struct amdgpu_device *adev,

				 u32 pcie_index, u32 pcie_data,

				 u32 reg_addr, u32 reg_data);

void amdgpu_device_indirect_wreg64(struct amdgpu_device *adev,

				   u32 pcie_index, u32 pcie_data,

				   u32 reg_addr, u64 reg_data);



bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type);

drivers/gpu/drm/amd/amdgpu/amdgpu_device.c

+18 −14
Original line number Diff line number Diff line
@@ -676,20 +676,20 @@ void amdgpu_mm_wdoorbell64(struct amdgpu_device *adev, u32 index, u64 v) 
 * amdgpu_device_indirect_rreg - read an indirect register

 *

 * @adev: amdgpu_device pointer

 * @pcie_index: mmio register offset

 * @pcie_data: mmio register offset

 * @reg_addr: indirect register address to read from

 *

 * Returns the value of indirect register @reg_addr

 */

u32 amdgpu_device_indirect_rreg(struct amdgpu_device *adev,

				u32 pcie_index, u32 pcie_data,

				u32 reg_addr)

{

	unsigned long flags;

	u32 r;

	unsigned long flags, pcie_index, pcie_data;

	void __iomem *pcie_index_offset;

	void __iomem *pcie_data_offset;

	u32 r;



	pcie_index = adev->nbio.funcs->get_pcie_index_offset(adev);

	pcie_data = adev->nbio.funcs->get_pcie_data_offset(adev);



	spin_lock_irqsave(&adev->pcie_idx_lock, flags);

	pcie_index_offset = (void __iomem *)adev->rmmio + pcie_index * 4;
@@ -707,20 +707,20 @@ u32 amdgpu_device_indirect_rreg(struct amdgpu_device *adev, 
 * amdgpu_device_indirect_rreg64 - read a 64bits indirect register

 *

 * @adev: amdgpu_device pointer

 * @pcie_index: mmio register offset

 * @pcie_data: mmio register offset

 * @reg_addr: indirect register address to read from

 *

 * Returns the value of indirect register @reg_addr

 */

u64 amdgpu_device_indirect_rreg64(struct amdgpu_device *adev,

				  u32 pcie_index, u32 pcie_data,

				  u32 reg_addr)

{

	unsigned long flags;

	u64 r;

	unsigned long flags, pcie_index, pcie_data;

	void __iomem *pcie_index_offset;

	void __iomem *pcie_data_offset;

	u64 r;



	pcie_index = adev->nbio.funcs->get_pcie_index_offset(adev);

	pcie_data = adev->nbio.funcs->get_pcie_data_offset(adev);



	spin_lock_irqsave(&adev->pcie_idx_lock, flags);

	pcie_index_offset = (void __iomem *)adev->rmmio + pcie_index * 4;
@@ -750,13 +750,15 @@ u64 amdgpu_device_indirect_rreg64(struct amdgpu_device *adev, 
 *

 */

void amdgpu_device_indirect_wreg(struct amdgpu_device *adev,

				 u32 pcie_index, u32 pcie_data,

				 u32 reg_addr, u32 reg_data)

{

	unsigned long flags;

	unsigned long flags, pcie_index, pcie_data;

	void __iomem *pcie_index_offset;

	void __iomem *pcie_data_offset;



	pcie_index = adev->nbio.funcs->get_pcie_index_offset(adev);

	pcie_data = adev->nbio.funcs->get_pcie_data_offset(adev);



	spin_lock_irqsave(&adev->pcie_idx_lock, flags);

	pcie_index_offset = (void __iomem *)adev->rmmio + pcie_index * 4;

	pcie_data_offset = (void __iomem *)adev->rmmio + pcie_data * 4;
@@ -779,13 +781,15 @@ void amdgpu_device_indirect_wreg(struct amdgpu_device *adev, 
 *

 */

void amdgpu_device_indirect_wreg64(struct amdgpu_device *adev,

				   u32 pcie_index, u32 pcie_data,

				   u32 reg_addr, u64 reg_data)

{

	unsigned long flags;

	unsigned long flags, pcie_index, pcie_data;

	void __iomem *pcie_index_offset;

	void __iomem *pcie_data_offset;



	pcie_index = adev->nbio.funcs->get_pcie_index_offset(adev);

	pcie_data = adev->nbio.funcs->get_pcie_data_offset(adev);



	spin_lock_irqsave(&adev->pcie_idx_lock, flags);

	pcie_index_offset = (void __iomem *)adev->rmmio + pcie_index * 4;

	pcie_data_offset = (void __iomem *)adev->rmmio + pcie_data * 4;

drivers/gpu/drm/amd/amdgpu/nv.c

+4 −45
Original line number Diff line number Diff line
@@ -280,47 +280,6 @@ static int nv_query_video_codecs(struct amdgpu_device *adev, bool encode, 
	}

}



/*

 * Indirect registers accessor

 */

static u32 nv_pcie_rreg(struct amdgpu_device *adev, u32 reg)

{

	unsigned long address, data;

	address = adev->nbio.funcs->get_pcie_index_offset(adev);

	data = adev->nbio.funcs->get_pcie_data_offset(adev);



	return amdgpu_device_indirect_rreg(adev, address, data, reg);

}



static void nv_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v)

{

	unsigned long address, data;



	address = adev->nbio.funcs->get_pcie_index_offset(adev);

	data = adev->nbio.funcs->get_pcie_data_offset(adev);



	amdgpu_device_indirect_wreg(adev, address, data, reg, v);

}



static u64 nv_pcie_rreg64(struct amdgpu_device *adev, u32 reg)

{

	unsigned long address, data;

	address = adev->nbio.funcs->get_pcie_index_offset(adev);

	data = adev->nbio.funcs->get_pcie_data_offset(adev);



	return amdgpu_device_indirect_rreg64(adev, address, data, reg);

}



static void nv_pcie_wreg64(struct amdgpu_device *adev, u32 reg, u64 v)

{

	unsigned long address, data;



	address = adev->nbio.funcs->get_pcie_index_offset(adev);

	data = adev->nbio.funcs->get_pcie_data_offset(adev);



	amdgpu_device_indirect_wreg64(adev, address, data, reg, v);

}



static u32 nv_didt_rreg(struct amdgpu_device *adev, u32 reg)

{

	unsigned long flags, address, data;
@@ -738,10 +697,10 @@ static int nv_common_early_init(void *handle) 
	}

	adev->smc_rreg = NULL;

	adev->smc_wreg = NULL;

	adev->pcie_rreg = &nv_pcie_rreg;

	adev->pcie_wreg = &nv_pcie_wreg;

	adev->pcie_rreg64 = &nv_pcie_rreg64;

	adev->pcie_wreg64 = &nv_pcie_wreg64;

	adev->pcie_rreg = &amdgpu_device_indirect_rreg;

	adev->pcie_wreg = &amdgpu_device_indirect_wreg;

	adev->pcie_rreg64 = &amdgpu_device_indirect_rreg64;

	adev->pcie_wreg64 = &amdgpu_device_indirect_wreg64;

	adev->pciep_rreg = amdgpu_device_pcie_port_rreg;

	adev->pciep_wreg = amdgpu_device_pcie_port_wreg;

drivers/gpu/drm/amd/amdgpu/soc15.c

+4 −45
Original line number Diff line number Diff line
@@ -191,47 +191,6 @@ static int soc15_query_video_codecs(struct amdgpu_device *adev, bool encode, 
	}

}



/*

 * Indirect registers accessor

 */

static u32 soc15_pcie_rreg(struct amdgpu_device *adev, u32 reg)

{

	unsigned long address, data;

	address = adev->nbio.funcs->get_pcie_index_offset(adev);

	data = adev->nbio.funcs->get_pcie_data_offset(adev);



	return amdgpu_device_indirect_rreg(adev, address, data, reg);

}



static void soc15_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v)

{

	unsigned long address, data;



	address = adev->nbio.funcs->get_pcie_index_offset(adev);

	data = adev->nbio.funcs->get_pcie_data_offset(adev);



	amdgpu_device_indirect_wreg(adev, address, data, reg, v);

}



static u64 soc15_pcie_rreg64(struct amdgpu_device *adev, u32 reg)

{

	unsigned long address, data;

	address = adev->nbio.funcs->get_pcie_index_offset(adev);

	data = adev->nbio.funcs->get_pcie_data_offset(adev);



	return amdgpu_device_indirect_rreg64(adev, address, data, reg);

}



static void soc15_pcie_wreg64(struct amdgpu_device *adev, u32 reg, u64 v)

{

	unsigned long address, data;



	address = adev->nbio.funcs->get_pcie_index_offset(adev);

	data = adev->nbio.funcs->get_pcie_data_offset(adev);



	amdgpu_device_indirect_wreg64(adev, address, data, reg, v);

}



static u32 soc15_uvd_ctx_rreg(struct amdgpu_device *adev, u32 reg)

{

	unsigned long flags, address, data;
@@ -936,10 +895,10 @@ static int soc15_common_early_init(void *handle) 
	}

	adev->smc_rreg = NULL;

	adev->smc_wreg = NULL;

	adev->pcie_rreg = &soc15_pcie_rreg;

	adev->pcie_wreg = &soc15_pcie_wreg;

	adev->pcie_rreg64 = &soc15_pcie_rreg64;

	adev->pcie_wreg64 = &soc15_pcie_wreg64;

	adev->pcie_rreg = &amdgpu_device_indirect_rreg;

	adev->pcie_wreg = &amdgpu_device_indirect_wreg;

	adev->pcie_rreg64 = &amdgpu_device_indirect_rreg64;

	adev->pcie_wreg64 = &amdgpu_device_indirect_wreg64;

	adev->uvd_ctx_rreg = &soc15_uvd_ctx_rreg;

	adev->uvd_ctx_wreg = &soc15_uvd_ctx_wreg;

	adev->didt_rreg = &soc15_didt_rreg;

drivers/gpu/drm/amd/amdgpu/soc21.c

+4 −44
Original line number Diff line number Diff line
@@ -196,46 +196,6 @@ static int soc21_query_video_codecs(struct amdgpu_device *adev, bool encode, 
		return -EINVAL;

	}

}

/*

 * Indirect registers accessor

 */

static u32 soc21_pcie_rreg(struct amdgpu_device *adev, u32 reg)

{

	unsigned long address, data;

	address = adev->nbio.funcs->get_pcie_index_offset(adev);

	data = adev->nbio.funcs->get_pcie_data_offset(adev);



	return amdgpu_device_indirect_rreg(adev, address, data, reg);

}



static void soc21_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v)

{

	unsigned long address, data;



	address = adev->nbio.funcs->get_pcie_index_offset(adev);

	data = adev->nbio.funcs->get_pcie_data_offset(adev);



	amdgpu_device_indirect_wreg(adev, address, data, reg, v);

}



static u64 soc21_pcie_rreg64(struct amdgpu_device *adev, u32 reg)

{

	unsigned long address, data;

	address = adev->nbio.funcs->get_pcie_index_offset(adev);

	data = adev->nbio.funcs->get_pcie_data_offset(adev);



	return amdgpu_device_indirect_rreg64(adev, address, data, reg);

}



static void soc21_pcie_wreg64(struct amdgpu_device *adev, u32 reg, u64 v)

{

	unsigned long address, data;



	address = adev->nbio.funcs->get_pcie_index_offset(adev);

	data = adev->nbio.funcs->get_pcie_data_offset(adev);



	amdgpu_device_indirect_wreg64(adev, address, data, reg, v);

}



static u32 soc21_didt_rreg(struct amdgpu_device *adev, u32 reg)

{
@@ -650,10 +610,10 @@ static int soc21_common_early_init(void *handle) 
	adev->rmmio_remap.bus_addr = adev->rmmio_base + MMIO_REG_HOLE_OFFSET;

	adev->smc_rreg = NULL;

	adev->smc_wreg = NULL;

	adev->pcie_rreg = &soc21_pcie_rreg;

	adev->pcie_wreg = &soc21_pcie_wreg;

	adev->pcie_rreg64 = &soc21_pcie_rreg64;

	adev->pcie_wreg64 = &soc21_pcie_wreg64;

	adev->pcie_rreg = &amdgpu_device_indirect_rreg;

	adev->pcie_wreg = &amdgpu_device_indirect_wreg;

	adev->pcie_rreg64 = &amdgpu_device_indirect_rreg64;

	adev->pcie_wreg64 = &amdgpu_device_indirect_wreg64;

	adev->pciep_rreg = amdgpu_device_pcie_port_rreg;

	adev->pciep_wreg = amdgpu_device_pcie_port_wreg;