Commit 66ae6aed authored by William Zhang's avatar William Zhang Committed by Florian Fainelli
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ARM: dts: Add DTS files for bcmbca SoC BCM6855 



Add DTS for ARMv7 based broadband SoC BCM6855. bcm6855.dtsi is the SoC
description DTS header and bcm96855.dts is a simple DTS file for
Broadcom BCM96855 Reference board that only enable the UART port.

Signed-off-by: default avatarWilliam Zhang <william.zhang@broadcom.com>
Signed-off-by: default avatarFlorian Fainelli <f.fainelli@gmail.com>
parent bd42ce0d

arch/arm/boot/dts/Makefile

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@@ -185,6 +185,7 @@ dtb-$(CONFIG_ARCH_BCMBCA) += \ 
	bcm947622.dtb \

	bcm963178.dtb \

	bcm96846.dtb \

	bcm96855.dtb \

	bcm96878.dtb

dtb-$(CONFIG_ARCH_CLPS711X) += \

	ep7211-edb7211.dtb

arch/arm/boot/dts/bcm6855.dtsi

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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)

/*

 * Copyright 2022 Broadcom Ltd.

 */



#include <dt-bindings/interrupt-controller/arm-gic.h>

#include <dt-bindings/interrupt-controller/irq.h>



/ {

	compatible = "brcm,bcm6855", "brcm,bcmbca";

	#address-cells = <1>;

	#size-cells = <1>;



	interrupt-parent = <&gic>;



	cpus {

		#address-cells = <1>;

		#size-cells = <0>;



		CA7_0: cpu@0 {

			device_type = "cpu";

			compatible = "arm,cortex-a7";

			reg = <0x0>;

			next-level-cache = <&L2_0>;

			enable-method = "psci";

		};



		CA7_1: cpu@1 {

			device_type = "cpu";

			compatible = "arm,cortex-a7";

			reg = <0x1>;

			next-level-cache = <&L2_0>;

			enable-method = "psci";

		};



		CA7_2: cpu@2 {

			device_type = "cpu";

			compatible = "arm,cortex-a7";

			reg = <0x2>;

			next-level-cache = <&L2_0>;

			enable-method = "psci";

		};



		L2_0: l2-cache0 {

			compatible = "cache";

		};

	};



	timer {

		compatible = "arm,armv7-timer";

		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(3) | IRQ_TYPE_LEVEL_LOW)>,

			<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(3) | IRQ_TYPE_LEVEL_LOW)>,

			<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(3) | IRQ_TYPE_LEVEL_LOW)>,

			<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(3) | IRQ_TYPE_LEVEL_LOW)>;

		arm,cpu-registers-not-fw-configured;

	};



	pmu: pmu {

		compatible = "arm,cortex-a7-pmu";

		interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,

			<GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,

			<GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;

		interrupt-affinity = <&CA7_0>, <&CA7_1>, <&CA7_2>;

	};



	clocks: clocks {

		periph_clk: periph-clk {

			compatible = "fixed-clock";

			#clock-cells = <0>;

			clock-frequency = <200000000>;

		};



		uart_clk: uart-clk {

			compatible = "fixed-factor-clock";

			#clock-cells = <0>;

			clocks = <&periph_clk>;

			clock-div = <4>;

			clock-mult = <1>;

		};

	};



	psci {

		compatible = "arm,psci-0.2";

		method = "smc";

	};



	axi@81000000 {

		compatible = "simple-bus";

		#address-cells = <1>;

		#size-cells = <1>;

		ranges = <0 0x81000000 0x8000>;



		gic: interrupt-controller@1000 {

			compatible = "arm,cortex-a7-gic";

			#interrupt-cells = <3>;

			interrupt-controller;

			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(3) | IRQ_TYPE_LEVEL_HIGH)>;

			reg = <0x1000 0x1000>,

				<0x2000 0x2000>,

				<0x4000 0x2000>,

				<0x6000 0x2000>;

		};

	};



	bus@ff800000 {

		compatible = "simple-bus";

		#address-cells = <1>;

		#size-cells = <1>;

		ranges = <0 0xff800000 0x800000>;



		uart0: serial@12000 {

			compatible = "arm,pl011", "arm,primecell";

			reg = <0x12000 0x1000>;

			interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&uart_clk>, <&uart_clk>;

			clock-names = "uartclk", "apb_pclk";

			status = "disabled";

		};

	};

};

arch/arm/boot/dts/bcm96855.dts

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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)

/*

 * Copyright 2019 Broadcom Ltd.

 */



/dts-v1/;



#include "bcm6855.dtsi"



/ {

	model = "Broadcom BCM96855 Reference Board";

	compatible = "brcm,bcm96855", "brcm,bcm6855", "brcm,bcmbca";



	aliases {

		serial0 = &uart0;

	};



	chosen {

		stdout-path = "serial0:115200n8";

	};



	memory@0 {

		device_type = "memory";

		reg = <0x0 0x08000000>;

	};

};



&uart0 {

	status = "okay";

};