Unverified Commit 67270fb3 authored by Heiko Stuebner's avatar Heiko Stuebner Committed by Palmer Dabbelt
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RISC-V: don't parse dt/acpi isa string to get rv32/rv64 



When filling hwcap the kernel already expects the isa string to start with
rv32 if CONFIG_32BIT and rv64 if CONFIG_64BIT.

So when recreating the runtime isa-string we can also just go the other way
to get the correct starting point for it.

Signed-off-by: default avatarHeiko Stuebner <heiko.stuebner@vrull.eu>
Reviewed-by: default avatarAndrew Jones <ajones@ventanamicro.com>
Reviewed-by: default avatarEvan Green <evan@rivosinc.com>
Co-developed-by: default avatarConor Dooley <conor.dooley@microchip.com>
Signed-off-by: default avatarConor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20230713-masculine-saddlebag-67a94966b091@wendy


Signed-off-by: default avatarPalmer Dabbelt <palmer@rivosinc.com>
parent 23059893

arch/riscv/kernel/cpu.c

+9 −12
Original line number Original line Diff line number Diff line
@@ -257,13 +257,16 @@ static void print_isa_ext(struct seq_file *f) 
 */

 */

static const char base_riscv_exts[13] = "imafdqcbkjpvh";

static const char base_riscv_exts[13] = "imafdqcbkjpvh";





static void print_isa(struct seq_file *f, const char *isa)

static void print_isa(struct seq_file *f)

{

{

	int i;

	int i;





	seq_puts(f, "isa\t\t: ");

	seq_puts(f, "isa\t\t: ");

	/* Print the rv[64/32] part */

	if (IS_ENABLED(CONFIG_32BIT))

	seq_write(f, isa, 4);

		seq_write(f, "rv32", 4);

	else

		seq_write(f, "rv64", 4);



	for (i = 0; i < sizeof(base_riscv_exts); i++) {

	for (i = 0; i < sizeof(base_riscv_exts); i++) {

		if (__riscv_isa_extension_available(NULL, base_riscv_exts[i] - 'a'))

		if (__riscv_isa_extension_available(NULL, base_riscv_exts[i] - 'a'))

			/* Print only enabled the base ISA extensions */

			/* Print only enabled the base ISA extensions */
@@ -320,27 +323,21 @@ static int c_show(struct seq_file *m, void *v) 
	unsigned long cpu_id = (unsigned long)v - 1;

	unsigned long cpu_id = (unsigned long)v - 1;

	struct riscv_cpuinfo *ci = per_cpu_ptr(&riscv_cpuinfo, cpu_id);

	struct riscv_cpuinfo *ci = per_cpu_ptr(&riscv_cpuinfo, cpu_id);

	struct device_node *node;

	struct device_node *node;

	const char *compat, *isa;

	const char *compat;





	seq_printf(m, "processor\t: %lu\n", cpu_id);

	seq_printf(m, "processor\t: %lu\n", cpu_id);

	seq_printf(m, "hart\t\t: %lu\n", cpuid_to_hartid_map(cpu_id));

	seq_printf(m, "hart\t\t: %lu\n", cpuid_to_hartid_map(cpu_id));

	print_isa(m);

	print_mmu(m);





	if (acpi_disabled) {

	if (acpi_disabled) {

		node = of_get_cpu_node(cpu_id, NULL);

		node = of_get_cpu_node(cpu_id, NULL);

		if (!of_property_read_string(node, "riscv,isa", &isa))

			print_isa(m, isa);





		print_mmu(m);

		if (!of_property_read_string(node, "compatible", &compat) &&

		if (!of_property_read_string(node, "compatible", &compat) &&

		    strcmp(compat, "riscv"))

		    strcmp(compat, "riscv"))

			seq_printf(m, "uarch\t\t: %s\n", compat);

			seq_printf(m, "uarch\t\t: %s\n", compat);





		of_node_put(node);

		of_node_put(node);

	} else {

		if (!acpi_get_riscv_isa(NULL, cpu_id, &isa))

			print_isa(m, isa);



		print_mmu(m);

	}

	}





	seq_printf(m, "mvendorid\t: 0x%lx\n", ci->mvendorid);

	seq_printf(m, "mvendorid\t: 0x%lx\n", ci->mvendorid);