Loading arch/arm64/boot/dts/intel/socfpga_agilex.dtsi +12 −0 Original line number Diff line number Diff line Loading @@ -249,6 +249,18 @@ mmc: dwmmc0@ff808000 { status = "disabled"; }; nand: nand@ffb90000 { #address-cells = <1>; #size-cells = <0>; compatible = "altr,socfpga-denali-nand"; reg = <0xffb90000 0x10000>, <0xffb80000 0x1000>; reg-names = "nand_data", "denali_reg"; interrupts = <0 97 4>; resets = <&rst NAND_RESET>, <&rst NAND_OCP_RESET>; status = "disabled"; }; ocram: sram@ffe00000 { compatible = "mmio-sram"; reg = <0xffe00000 0x40000>; Loading Loading
arch/arm64/boot/dts/intel/socfpga_agilex.dtsi +12 −0 Original line number Diff line number Diff line Loading @@ -249,6 +249,18 @@ mmc: dwmmc0@ff808000 { status = "disabled"; }; nand: nand@ffb90000 { #address-cells = <1>; #size-cells = <0>; compatible = "altr,socfpga-denali-nand"; reg = <0xffb90000 0x10000>, <0xffb80000 0x1000>; reg-names = "nand_data", "denali_reg"; interrupts = <0 97 4>; resets = <&rst NAND_RESET>, <&rst NAND_OCP_RESET>; status = "disabled"; }; ocram: sram@ffe00000 { compatible = "mmio-sram"; reg = <0xffe00000 0x40000>; Loading