Commit 6983469c authored by Xiaojie Yuan's avatar Xiaojie Yuan Committed by Alex Deucher
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drm/amdgpu/gfx10: add gfx config for navi12 



got from mmCP_MAX_CONTEXT and mmPA_SC_FIFO_SIZE

v2: squash all navi asics together because the
settings are the same.

Signed-off-by: default avatarXiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: default avatarHawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 59ab8c29

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

+2 −8
Original line number Diff line number Diff line
@@ -1095,18 +1095,12 @@ static void gfx_v10_0_gpu_early_init(struct amdgpu_device *adev) 


	switch (adev->asic_type) {

	case CHIP_NAVI10:

		adev->gfx.config.max_hw_contexts = 8;

		adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;

		adev->gfx.config.sc_prim_fifo_size_backend = 0x100;

		adev->gfx.config.sc_hiz_tile_fifo_size = 0;

		adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;

		gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG);

		break;

	case CHIP_NAVI14:

	case CHIP_NAVI12:

		adev->gfx.config.max_hw_contexts = 8;

		adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;

		adev->gfx.config.sc_prim_fifo_size_backend = 0x100;

		adev->gfx.config.sc_hiz_tile_fifo_size = 0x0;

		adev->gfx.config.sc_hiz_tile_fifo_size = 0;

		adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;

		gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG);

		break;