Commit 6bbb1370 authored by Stanislaw Gruszka's avatar Stanislaw Gruszka
Browse files

iwlegacy: move iwl-3945-{,hw,fh,debugfs}.h to 3945.h 



Signed-off-by: default avatarStanislaw Gruszka <sgruszka@redhat.com>
parent af038f40

drivers/net/wireless/iwlegacy/3945-debug.c

+3 −2
Original line number Diff line number Diff line
@@ -26,8 +26,9 @@ 
 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497

 *****************************************************************************/



#include "iwl-3945-debugfs.h"



#include "iwl-dev.h"

#include "iwl-core.h"

#include "3945.h"



static int il3945_stats_flag(struct il_priv *il, char *buf, int bufsz)

{

drivers/net/wireless/iwlegacy/3945-mac.c

+1 −2
Original line number Diff line number Diff line
@@ -52,10 +52,9 @@ 
#define DRV_NAME	"iwl3945"



#include "iwl-fh.h"

#include "iwl-3945-fh.h"

#include "iwl-commands.h"

#include "iwl-sta.h"

#include "iwl-3945.h"

#include "3945.h"

#include "iwl-core.h"

#include "iwl-helpers.h"

#include "iwl-dev.h"

drivers/net/wireless/iwlegacy/3945-rs.c

+1 −1
Original line number Diff line number Diff line
@@ -37,7 +37,7 @@ 
#include <linux/workqueue.h>



#include "iwl-commands.h"

#include "iwl-3945.h"

#include "3945.h"

#include "iwl-sta.h"



#define RS_NAME "iwl-3945-rs"

drivers/net/wireless/iwlegacy/3945.c

+1 −3
Original line number Diff line number Diff line
@@ -40,15 +40,13 @@ 
#include <net/mac80211.h>



#include "iwl-fh.h"

#include "iwl-3945-fh.h"

#include "iwl-commands.h"

#include "iwl-sta.h"

#include "iwl-3945.h"

#include "iwl-eeprom.h"

#include "iwl-core.h"

#include "iwl-helpers.h"

#include "iwl-led.h"

#include "iwl-3945-debugfs.h"

#include "3945.h"



/* Send led command */

static int il3945_send_led_cmd(struct il_priv *il,

drivers/net/wireless/iwlegacy/iwl-3945.h→drivers/net/wireless/iwlegacy/3945.h

+368 −9
Original line number Diff line number Diff line
@@ -23,11 +23,6 @@ 
 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497

 *

 *****************************************************************************/

/*

 * Please use this file (iwl-3945.h) for driver implementation definitions.

 * Please use iwl-3945-commands.h for uCode API definitions.

 * Please use iwl-3945-hw.h for hardware-related definitions.

 */



#ifndef __il_3945_h__

#define __il_3945_h__
@@ -42,11 +37,11 @@ extern const struct pci_device_id il3945_hw_card_ids[]; 
#include "iwl-csr.h"

#include "iwl-prph.h"

#include "iwl-fh.h"

#include "iwl-3945-hw.h"

#include "iwl-debug.h"

#include "iwl-power.h"

#include "iwl-dev.h"

#include "iwl-led.h"

#include "iwl-eeprom.h"



/* Highest firmware API version supported */

#define IL3945_UCODE_API_MAX 2
@@ -282,9 +277,6 @@ extern u8 il3945_hw_find_station(struct il_priv *il, const u8 *bssid); 


extern struct ieee80211_ops il3945_hw_ops;



/*

 * Forward declare iwl-3945.c functions for iwl3945-base.c

 */

extern __le32 il3945_get_antenna_flags(const struct il_priv *il);

extern int il3945_init_hw_rate_table(struct il_priv *il);

extern void il3945_reg_txpower_periodic(struct il_priv *il);
@@ -302,6 +294,373 @@ void il3945_post_scan(struct il_priv *il); 
/* rates */

extern const struct il3945_rate_info il3945_rates[RATE_COUNT_3945];







/* RSSI to dBm */

#define IL39_RSSI_OFFSET	95



/*

 * EEPROM related constants, enums, and structures.

 */

#define EEPROM_SKU_CAP_OP_MODE_MRC                      (1 << 7)



/*

 * Mapping of a Tx power level, at factory calibration temperature,

 *   to a radio/DSP gain table idx.

 * One for each of 5 "sample" power levels in each band.

 * v_det is measured at the factory, using the 3945's built-in power amplifier

 *   (PA) output voltage detector.  This same detector is used during Tx of

 *   long packets in normal operation to provide feedback as to proper output

 *   level.

 * Data copied from EEPROM.

 * DO NOT ALTER THIS STRUCTURE!!!

 */

struct il3945_eeprom_txpower_sample {

	u8 gain_idx;		/* idx into power (gain) setup table ... */

	s8 power;		/* ... for this pwr level for this chnl group */

	u16 v_det;		/* PA output voltage */

} __packed;



/*

 * Mappings of Tx power levels -> nominal radio/DSP gain table idxes.

 * One for each channel group (a.k.a. "band") (1 for BG, 4 for A).

 * Tx power setup code interpolates between the 5 "sample" power levels

 *    to determine the nominal setup for a requested power level.

 * Data copied from EEPROM.

 * DO NOT ALTER THIS STRUCTURE!!!

 */

struct il3945_eeprom_txpower_group {

	struct il3945_eeprom_txpower_sample samples[5];  /* 5 power levels */

	s32 a, b, c, d, e;	/* coefficients for voltage->power

				 * formula (signed) */

	s32 Fa, Fb, Fc, Fd, Fe;	/* these modify coeffs based on

				 * frequency (signed) */

	s8 saturation_power;	/* highest power possible by h/w in this

				 * band */

	u8 group_channel;	/* "representative" channel # in this band */

	s16 temperature;	/* h/w temperature at factory calib this band

				 * (signed) */

} __packed;



/*

 * Temperature-based Tx-power compensation data, not band-specific.

 * These coefficients are use to modify a/b/c/d/e coeffs based on

 *   difference between current temperature and factory calib temperature.

 * Data copied from EEPROM.

 */

struct il3945_eeprom_temperature_corr {

	u32 Ta;

	u32 Tb;

	u32 Tc;

	u32 Td;

	u32 Te;

} __packed;



/*

 * EEPROM map

 */

struct il3945_eeprom {

	u8 reserved0[16];

	u16 device_id;	/* abs.ofs: 16 */

	u8 reserved1[2];

	u16 pmc;		/* abs.ofs: 20 */

	u8 reserved2[20];

	u8 mac_address[6];	/* abs.ofs: 42 */

	u8 reserved3[58];

	u16 board_revision;	/* abs.ofs: 106 */

	u8 reserved4[11];

	u8 board_pba_number[9];	/* abs.ofs: 119 */

	u8 reserved5[8];

	u16 version;		/* abs.ofs: 136 */

	u8 sku_cap;		/* abs.ofs: 138 */

	u8 leds_mode;		/* abs.ofs: 139 */

	u16 oem_mode;

	u16 wowlan_mode;	/* abs.ofs: 142 */

	u16 leds_time_interval;	/* abs.ofs: 144 */

	u8 leds_off_time;	/* abs.ofs: 146 */

	u8 leds_on_time;	/* abs.ofs: 147 */

	u8 almgor_m_version;	/* abs.ofs: 148 */

	u8 antenna_switch_type;	/* abs.ofs: 149 */

	u8 reserved6[42];

	u8 sku_id[4];		/* abs.ofs: 192 */



/*

 * Per-channel regulatory data.

 *

 * Each channel that *might* be supported by 3945 has a fixed location

 * in EEPROM containing EEPROM_CHANNEL_* usage flags (LSB) and max regulatory

 * txpower (MSB).

 *

 * Entries immediately below are for 20 MHz channel width.

 *

 * 2.4 GHz channels 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14

 */

	u16 band_1_count;	/* abs.ofs: 196 */

	struct il_eeprom_channel band_1_channels[14];  /* abs.ofs: 198 */



/*

 * 4.9 GHz channels 183, 184, 185, 187, 188, 189, 192, 196,

 * 5.0 GHz channels 7, 8, 11, 12, 16

 * (4915-5080MHz) (none of these is ever supported)

 */

	u16 band_2_count;	/* abs.ofs: 226 */

	struct il_eeprom_channel band_2_channels[13];  /* abs.ofs: 228 */



/*

 * 5.2 GHz channels 34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64

 * (5170-5320MHz)

 */

	u16 band_3_count;	/* abs.ofs: 254 */

	struct il_eeprom_channel band_3_channels[12];  /* abs.ofs: 256 */



/*

 * 5.5 GHz channels 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140

 * (5500-5700MHz)

 */

	u16 band_4_count;	/* abs.ofs: 280 */

	struct il_eeprom_channel band_4_channels[11];  /* abs.ofs: 282 */



/*

 * 5.7 GHz channels 145, 149, 153, 157, 161, 165

 * (5725-5825MHz)

 */

	u16 band_5_count;	/* abs.ofs: 304 */

	struct il_eeprom_channel band_5_channels[6];  /* abs.ofs: 306 */



	u8 reserved9[194];



/*

 * 3945 Txpower calibration data.

 */

#define IL_NUM_TX_CALIB_GROUPS 5

	struct il3945_eeprom_txpower_group groups[IL_NUM_TX_CALIB_GROUPS];

/* abs.ofs: 512 */

	struct il3945_eeprom_temperature_corr corrections;  /* abs.ofs: 832 */

	u8 reserved16[172];	/* fill out to full 1024 byte block */

} __packed;



#define IL3945_EEPROM_IMG_SIZE 1024



/* End of EEPROM */



#define PCI_CFG_REV_ID_BIT_BASIC_SKU                (0x40)	/* bit 6    */

#define PCI_CFG_REV_ID_BIT_RTP                      (0x80)	/* bit 7    */



/* 4 DATA + 1 CMD. There are 2 HCCA queues that are not used. */

#define IL39_NUM_QUEUES        5

#define IL39_CMD_QUEUE_NUM	4



#define IL_DEFAULT_TX_RETRY  15



/*********************************************/



#define RFD_SIZE                              4

#define NUM_TFD_CHUNKS                        4



#define RX_QUEUE_SIZE                         256

#define RX_QUEUE_MASK                         255

#define RX_QUEUE_SIZE_LOG                     8



#define TFD_CTL_COUNT_SET(n)       (n << 24)

#define TFD_CTL_COUNT_GET(ctl)     ((ctl >> 24) & 7)

#define TFD_CTL_PAD_SET(n)         (n << 28)

#define TFD_CTL_PAD_GET(ctl)       (ctl >> 28)



/* Sizes and addresses for instruction and data memory (SRAM) in

 * 3945's embedded processor.  Driver access is via HBUS_TARG_MEM_* regs. */

#define IL39_RTC_INST_LOWER_BOUND		(0x000000)

#define IL39_RTC_INST_UPPER_BOUND		(0x014000)



#define IL39_RTC_DATA_LOWER_BOUND		(0x800000)

#define IL39_RTC_DATA_UPPER_BOUND		(0x808000)



#define IL39_RTC_INST_SIZE (IL39_RTC_INST_UPPER_BOUND - \

				IL39_RTC_INST_LOWER_BOUND)

#define IL39_RTC_DATA_SIZE (IL39_RTC_DATA_UPPER_BOUND - \

				IL39_RTC_DATA_LOWER_BOUND)



#define IL39_MAX_INST_SIZE IL39_RTC_INST_SIZE

#define IL39_MAX_DATA_SIZE IL39_RTC_DATA_SIZE



/* Size of uCode instruction memory in bootstrap state machine */

#define IL39_MAX_BSM_SIZE IL39_RTC_INST_SIZE



static inline int il3945_hw_valid_rtc_data_addr(u32 addr)

{

	return (addr >= IL39_RTC_DATA_LOWER_BOUND &&

		addr < IL39_RTC_DATA_UPPER_BOUND);

}



/* Base physical address of il3945_shared is provided to FH_TSSR_CBB_BASE

 * and &il3945_shared.rx_read_ptr[0] is provided to FH_RCSR_RPTR_ADDR(0) */

struct il3945_shared {

	__le32 tx_base_ptr[8];

} __packed;



static inline u8 il3945_hw_get_rate(__le16 rate_n_flags)

{

	return le16_to_cpu(rate_n_flags) & 0xFF;

}



static inline u16 il3945_hw_get_rate_n_flags(__le16 rate_n_flags)

{

	return le16_to_cpu(rate_n_flags);

}



static inline __le16 il3945_hw_set_rate_n_flags(u8 rate, u16 flags)

{

	return cpu_to_le16((u16)rate|flags);

}



/************************************/

/* iwl3945 Flow Handler Definitions */

/************************************/



/**

 * This I/O area is directly read/writable by driver (e.g. Linux uses writel())

 * Addresses are offsets from device's PCI hardware base address.

 */

#define FH39_MEM_LOWER_BOUND                   (0x0800)

#define FH39_MEM_UPPER_BOUND                   (0x1000)



#define FH39_CBCC_TBL		(FH39_MEM_LOWER_BOUND + 0x140)

#define FH39_TFDB_TBL		(FH39_MEM_LOWER_BOUND + 0x180)

#define FH39_RCSR_TBL		(FH39_MEM_LOWER_BOUND + 0x400)

#define FH39_RSSR_TBL		(FH39_MEM_LOWER_BOUND + 0x4c0)

#define FH39_TCSR_TBL		(FH39_MEM_LOWER_BOUND + 0x500)

#define FH39_TSSR_TBL		(FH39_MEM_LOWER_BOUND + 0x680)



/* TFDB (Transmit Frame Buffer Descriptor) */

#define FH39_TFDB(_ch, buf)			(FH39_TFDB_TBL + \

						 ((_ch) * 2 + (buf)) * 0x28)

#define FH39_TFDB_CHNL_BUF_CTRL_REG(_ch)	(FH39_TFDB_TBL + 0x50 * (_ch))



/* CBCC channel is [0,2] */

#define FH39_CBCC(_ch)		(FH39_CBCC_TBL + (_ch) * 0x8)

#define FH39_CBCC_CTRL(_ch)	(FH39_CBCC(_ch) + 0x00)

#define FH39_CBCC_BASE(_ch)	(FH39_CBCC(_ch) + 0x04)



/* RCSR channel is [0,2] */

#define FH39_RCSR(_ch)			(FH39_RCSR_TBL + (_ch) * 0x40)

#define FH39_RCSR_CONFIG(_ch)		(FH39_RCSR(_ch) + 0x00)

#define FH39_RCSR_RBD_BASE(_ch)		(FH39_RCSR(_ch) + 0x04)

#define FH39_RCSR_WPTR(_ch)		(FH39_RCSR(_ch) + 0x20)

#define FH39_RCSR_RPTR_ADDR(_ch)	(FH39_RCSR(_ch) + 0x24)



#define FH39_RSCSR_CHNL0_WPTR		(FH39_RCSR_WPTR(0))



/* RSSR */

#define FH39_RSSR_CTRL			(FH39_RSSR_TBL + 0x000)

#define FH39_RSSR_STATUS		(FH39_RSSR_TBL + 0x004)



/* TCSR */

#define FH39_TCSR(_ch)			(FH39_TCSR_TBL + (_ch) * 0x20)

#define FH39_TCSR_CONFIG(_ch)		(FH39_TCSR(_ch) + 0x00)

#define FH39_TCSR_CREDIT(_ch)		(FH39_TCSR(_ch) + 0x04)

#define FH39_TCSR_BUFF_STTS(_ch)	(FH39_TCSR(_ch) + 0x08)



/* TSSR */

#define FH39_TSSR_CBB_BASE        (FH39_TSSR_TBL + 0x000)

#define FH39_TSSR_MSG_CONFIG      (FH39_TSSR_TBL + 0x008)

#define FH39_TSSR_TX_STATUS       (FH39_TSSR_TBL + 0x010)





/* DBM */



#define FH39_SRVC_CHNL                            (6)



#define FH39_RCSR_RX_CONFIG_REG_POS_RBDC_SIZE     (20)

#define FH39_RCSR_RX_CONFIG_REG_POS_IRQ_RBTH      (4)



#define FH39_RCSR_RX_CONFIG_REG_BIT_WR_STTS_EN    (0x08000000)



#define FH39_RCSR_RX_CONFIG_REG_VAL_DMA_CHNL_EN_ENABLE        (0x80000000)



#define FH39_RCSR_RX_CONFIG_REG_VAL_RDRBD_EN_ENABLE           (0x20000000)



#define FH39_RCSR_RX_CONFIG_REG_VAL_MAX_FRAG_SIZE_128		(0x01000000)



#define FH39_RCSR_RX_CONFIG_REG_VAL_IRQ_DEST_INT_HOST		(0x00001000)



#define FH39_RCSR_RX_CONFIG_REG_VAL_MSG_MODE_FH			(0x00000000)



#define FH39_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_TXF		(0x00000000)

#define FH39_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_DRIVER		(0x00000001)



#define FH39_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE_VAL	(0x00000000)

#define FH39_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL	(0x00000008)



#define FH39_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_IFTFD		(0x00200000)



#define FH39_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_NOINT		(0x00000000)



#define FH39_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE		(0x00000000)

#define FH39_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE		(0x80000000)



#define FH39_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID		(0x00004000)



#define FH39_TCSR_CHNL_TX_BUF_STS_REG_BIT_TFDB_WPTR		(0x00000001)



#define FH39_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TXPD_ON	(0xFF000000)

#define FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_TXPD_ON	(0x00FF0000)



#define FH39_TSSR_TX_MSG_CONFIG_REG_VAL_MAX_FRAG_SIZE_128B	(0x00000400)



#define FH39_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TFD_ON		(0x00000100)

#define FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_CBB_ON		(0x00000080)



#define FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RSP_WAIT_TH	(0x00000020)

#define FH39_TSSR_TX_MSG_CONFIG_REG_VAL_RSP_WAIT_TH		(0x00000005)



#define FH39_TSSR_TX_STATUS_REG_BIT_BUFS_EMPTY(_ch)	(BIT(_ch) << 24)

#define FH39_TSSR_TX_STATUS_REG_BIT_NO_PEND_REQ(_ch)	(BIT(_ch) << 16)



#define FH39_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(_ch) \

	(FH39_TSSR_TX_STATUS_REG_BIT_BUFS_EMPTY(_ch) | \

	 FH39_TSSR_TX_STATUS_REG_BIT_NO_PEND_REQ(_ch))



#define FH39_RSSR_CHNL0_RX_STATUS_CHNL_IDLE			(0x01000000)



struct il3945_tfd_tb {

	__le32 addr;

	__le32 len;

} __packed;



struct il3945_tfd {

	__le32 control_flags;

	struct il3945_tfd_tb tbs[4];

	u8 __pad[28];

} __packed;



#ifdef CONFIG_IWLEGACY_DEBUGFS

ssize_t il3945_ucode_rx_stats_read(struct file *file, char __user *user_buf,

				    size_t count, loff_t *ppos);

ssize_t il3945_ucode_tx_stats_read(struct file *file, char __user *user_buf,

				    size_t count, loff_t *ppos);

ssize_t il3945_ucode_general_stats_read(struct file *file,

					 char __user *user_buf, size_t count,

					 loff_t *ppos);

#else

static ssize_t il3945_ucode_rx_stats_read(struct file *file,

					   char __user *user_buf, size_t count,

					   loff_t *ppos)

{

	return 0;

}

static ssize_t il3945_ucode_tx_stats_read(struct file *file,

					   char __user *user_buf, size_t count,

					   loff_t *ppos)

{

	return 0;

}

static ssize_t il3945_ucode_general_stats_read(struct file *file,

						char __user *user_buf,

						size_t count, loff_t *ppos)

{

	return 0;

}

#endif



/* Requires full declaration of il_priv before including */

#include "iwl-io.h"