Commit 6cadd424 authored by Miquel Raynal's avatar Miquel Raynal
Browse files

Merge tag 'nand/for-5.18' into mtd/next 



Raw NAND core changes:
* Rework of_get_nand_bus_width()
* Remove of_get_nand_on_flash_bbt() wrapper
* Protect access to rawnand devices while in suspend
* bindings: Document the wp-gpios property

Rax NAND controller driver changes:
* atmel: Fix refcount issue in atmel_nand_controller_init
* nandsim:
  - Add NS_PAGE_BYTE_SHIFT macro to replace the repeat pattern
  - Merge repeat codes in ns_switch_state
  - Replace overflow check with kzalloc to single kcalloc
* rockchip: Fix platform_get_irq.cocci warning
* stm32_fmc2: Add NAND Write Protect support
* pl353: Set the nand chip node as the flash node
* brcmnand: Fix sparse warnings in bcma_nand
* omap_elm: Remove redundant variable 'errors'
* gpmi:
  - Support fast edo timings for mx28
  - Validate controller clock rate
  - Fix controller timings setting
* brcmnand:
  - Add BCMA shim
  - BCMA controller uses command shift of 0
  - Allow platform data instantation
  - Add platform data structure for BCMA
  - Allow working without interrupts
  - Move OF operations out of brcmnand_init_cs()
  - Avoid pdev in brcmnand_init_cs()
  - Allow SoC to provide I/O operations
  - Assign soc as early as possible

Onenand changes:
* Check for error irq

Signed-off-by: default avatarMiquel Raynal <miquel.raynal@bootlin.com>
parents 4e371d99 fecbd4a3

Documentation/devicetree/bindings/mtd/nand-controller.yaml

+7 −0
Original line number Diff line number Diff line
@@ -116,6 +116,13 @@ patternProperties: 
          Ready/Busy pins. Active state refers to the NAND ready state and

          should be set to GPIOD_ACTIVE_HIGH unless the signal is inverted.



      wp-gpios:

        description:

          Contains one GPIO descriptor for the Write Protect pin.

          Active state refers to the NAND Write Protect state and should be

          set to GPIOD_ACTIVE_LOW unless the signal is inverted.

        maxItems: 1



    required:

      - reg

MAINTAINERS

+1 −0
Original line number Diff line number Diff line
@@ -4026,6 +4026,7 @@ L: linux-mtd@lists.infradead.org 
L:	bcm-kernel-feedback-list@broadcom.com

S:	Maintained

F:	drivers/mtd/nand/raw/brcmnand/

F:	include/linux/platform_data/brcmnand.h









BROADCOM STB PCIE DRIVER









M:	Jim Quinlan <jim2101024@gmail.com>


































drivers/bcma/driver_chipcommon_nflash.c



+19
−1






























Original line number
Diff line number
Diff line







@@ -7,18 +7,28 @@

















#include "bcma_private.h"



















#include <linux/bitops.h>









#include <linux/platform_device.h>









#include <linux/platform_data/brcmnand.h>









#include <linux/bcma/bcma.h>



















/* Alternate NAND controller driver name in order to allow both bcm47xxnflash









 * and bcma_brcmnand to be built into the same kernel image.









 */









static const char *bcma_nflash_alt_name = "bcma_brcmnand";



















struct platform_device bcma_nflash_dev = {









	.name		= "bcma_nflash",









	.num_resources	= 0,









};



















static const char *probes[] = { "bcm47xxpart", NULL };



















/* Initialize NAND flash access */









int bcma_nflash_init(struct bcma_drv_cc *cc)









{









	struct bcma_bus *bus = cc->core->bus;









	u32 reg;



















	if (bus->chipinfo.id != BCMA_CHIP_ID_BCM4706 &&









	    cc->core->id.rev != 38) {










@@ -33,8 +43,16 @@ int bcma_nflash_init(struct bcma_drv_cc *cc)

















	cc->nflash.present = true;









	if (cc->core->id.rev == 38 &&









	    (cc->status & BCMA_CC_CHIPST_5357_NAND_BOOT))









	    (cc->status & BCMA_CC_CHIPST_5357_NAND_BOOT)) {









		cc->nflash.boot = true;









		/* Determine the chip select that is being used */









		reg = bcma_cc_read32(cc, BCMA_CC_NAND_CS_NAND_SELECT) & 0xff;









		cc->nflash.brcmnand_info.chip_select = ffs(reg) - 1;









		cc->nflash.brcmnand_info.part_probe_types = probes;









		cc->nflash.brcmnand_info.ecc_stepsize = 512;









		cc->nflash.brcmnand_info.ecc_strength = 1;









		bcma_nflash_dev.name = bcma_nflash_alt_name;









	}



















	/* Prepare platform device, but don't register it yet. It's too early,









	 * malloc (required by device_private_init) is not available yet. */


































drivers/mtd/nand/onenand/generic.c



+6
−1






























Original line number
Diff line number
Diff line







@@ -53,7 +53,12 @@ static int generic_onenand_probe(struct platform_device *pdev)







	}



















	info->onenand.mmcontrol = pdata ? pdata->mmcontrol : NULL;









	info->onenand.irq = platform_get_irq(pdev, 0);



















	err = platform_get_irq(pdev, 0);









	if (err < 0)









		goto out_iounmap;



















	info->onenand.irq = err;



















	info->mtd.dev.parent = &pdev->dev;









	info->mtd.priv = &info->onenand;


































drivers/mtd/nand/raw/Kconfig



+13
−0






























Original line number
Diff line number
Diff line







@@ -210,6 +210,19 @@ config MTD_NAND_BRCMNAND







	  originally designed for Set-Top Box but is used on various BCM7xxx,









	  BCM3xxx, BCM63xxx, iProc/Cygnus and more.



















if MTD_NAND_BRCMNAND



















config MTD_NAND_BRCMNAND_BCMA









	tristate "Broadcom BCMA NAND controller"









	depends on BCMA_NFLASH









	depends on BCMA









	help









	  Enables the BRCMNAND controller over BCMA on BCM47186/BCM5358 SoCs.









	  The glue driver will take care of performing the low-level I/O









	  operations to interface the BRCMNAND controller over the BCMA bus.



















endif # MTD_NAND_BRCMNAND



















config MTD_NAND_BCM47XXNFLASH









	tristate "BCM4706 BCMA NAND controller"









	depends on BCMA_NFLASH