Commit 6de663fe authored by Alex Wilson's avatar Alex Wilson Committed by Michal Simek
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ARM: zynq: DT: Add missing interrupt for L2 pl310 



Add pl310 interrupt to the Zynq devicetree.

Signed-off-by: default avatarAlex Wilson <alex.david.wilson@gmail.com>
Signed-off-by: default avatarMichal Simek <michal.simek@xilinx.com>
parent 1837649f

arch/arm/boot/dts/zynq-7000.dtsi

+1 −0
Original line number Original line Diff line number Diff line
@@ -139,6 +139,7 @@ intc: interrupt-controller@f8f01000 { 
		L2: cache-controller@f8f02000 {

		L2: cache-controller@f8f02000 {

			compatible = "arm,pl310-cache";

			compatible = "arm,pl310-cache";

			reg = <0xF8F02000 0x1000>;

			reg = <0xF8F02000 0x1000>;

			interrupts = <0 2 4>;

			arm,data-latency = <3 2 2>;

			arm,data-latency = <3 2 2>;

			arm,tag-latency = <2 2 2>;

			arm,tag-latency = <2 2 2>;

			cache-unified;

			cache-unified;