Commit 6fe90cc5 authored by Nícolas F. R. A. Prado's avatar Nícolas F. R. A. Prado Committed by Matthias Brugger
Browse files

arm64: dts: mediatek: mt8192-asurada: Add MFG0 domain supply 



The mfg0 power domain encompasses the whole GPU and its surrounding
glue logic. This power domain has a separate power rail.

Add its power supply for Asurada.

Signed-off-by: default avatarNícolas F. R. A. Prado <nfraprado@collabora.com>
[wenst@chromium.org: fix subject prefix and add commit message]
Signed-off-by: default avatarChen-Yu Tsai <wenst@chromium.org>
[Angelo: Reordered commits to address DVFS stability issues]
Signed-off-by: default avatarAngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: default avatarChen-Yu Tsai <wenst@chromium.org>
Tested-by: default avatarChen-Yu Tsai <wenst@chromium.org>
Link: https://lore.kernel.org/r/20230301095523.428461-10-angelogioacchino.delregno@collabora.com


Signed-off-by: default avatarMatthias Brugger <matthias.bgg@gmail.com>
parent 61348fe9

arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi

+4 −0
Original line number Diff line number Diff line
@@ -380,6 +380,10 @@ &i2c7 { 
	pinctrl-0 = <&i2c7_pins>;

};



&mfg0 {

	domain-supply = <&mt6315_7_vbuck1>;

};



&mipi_tx0 {

	status = "okay";

};

arch/arm64/boot/dts/mediatek/mt8192.dtsi

+1 −1
Original line number Diff line number Diff line
@@ -497,7 +497,7 @@ power-domain@MT8192_POWER_DOMAIN_CONN { 
					#power-domain-cells = <0>;

				};



				power-domain@MT8192_POWER_DOMAIN_MFG0 {

				mfg0: power-domain@MT8192_POWER_DOMAIN_MFG0 {

					reg = <MT8192_POWER_DOMAIN_MFG0>;

					clocks = <&topckgen CLK_TOP_MFG_PLL_SEL>,

						 <&topckgen CLK_TOP_MFG_REF_SEL>;