Commit 7054e4e0 authored by Ingo Molnar's avatar Ingo Molnar
Browse files

Merge branch 'perf/urgent' into perf/core, to pick up fixes 



With the cherry-picked perf/urgent commit merged separately we can now
merge all the fixes without conflicts.

Signed-off-by: default avatarIngo Molnar <mingo@kernel.org>
parents 5701dd1e c917e0f2

arch/x86/events/core.c

+1 −1
Original line number Diff line number Diff line
@@ -2118,7 +2118,7 @@ static int x86_pmu_event_init(struct perf_event *event) 
	}



	if (READ_ONCE(x86_pmu.attr_rdpmc) &&

	    !(event->hw.flags & PERF_X86_EVENT_FREERUNNING))

	    !(event->hw.flags & PERF_X86_EVENT_LARGE_PEBS))

		event->hw.flags |= PERF_X86_EVENT_RDPMC_ALLOWED;



	return err;

arch/x86/events/intel/core.c

+7 −7
Original line number Diff line number Diff line
@@ -2968,9 +2968,9 @@ static void intel_pebs_aliases_skl(struct perf_event *event) 
	return intel_pebs_aliases_precdist(event);

}



static unsigned long intel_pmu_free_running_flags(struct perf_event *event)

static unsigned long intel_pmu_large_pebs_flags(struct perf_event *event)

{

	unsigned long flags = x86_pmu.free_running_flags;

	unsigned long flags = x86_pmu.large_pebs_flags;



	if (event->attr.use_clockid)

		flags &= ~PERF_SAMPLE_TIME;
@@ -2992,8 +2992,8 @@ static int intel_pmu_hw_config(struct perf_event *event) 
		if (!event->attr.freq) {

			event->hw.flags |= PERF_X86_EVENT_AUTO_RELOAD;

			if (!(event->attr.sample_type &

			      ~intel_pmu_free_running_flags(event)))

				event->hw.flags |= PERF_X86_EVENT_FREERUNNING;

			      ~intel_pmu_large_pebs_flags(event)))

				event->hw.flags |= PERF_X86_EVENT_LARGE_PEBS;

		}

		if (x86_pmu.pebs_aliases)

			x86_pmu.pebs_aliases(event);
@@ -3210,7 +3210,7 @@ static u64 bdw_limit_period(struct perf_event *event, u64 left) 
			X86_CONFIG(.event=0xc0, .umask=0x01)) {

		if (left < 128)

			left = 128;

		left &= ~0x3fu;

		left &= ~0x3fULL;

	}

	return left;

}
@@ -3476,7 +3476,7 @@ static __initconst const struct x86_pmu core_pmu = { 
	.event_map		= intel_pmu_event_map,

	.max_events		= ARRAY_SIZE(intel_perfmon_event_map),

	.apic			= 1,

	.free_running_flags	= PEBS_FREERUNNING_FLAGS,

	.large_pebs_flags	= LARGE_PEBS_FLAGS,



	/*

	 * Intel PMCs cannot be accessed sanely above 32-bit width,
@@ -3519,7 +3519,7 @@ static __initconst const struct x86_pmu intel_pmu = { 
	.event_map		= intel_pmu_event_map,

	.max_events		= ARRAY_SIZE(intel_perfmon_event_map),

	.apic			= 1,

	.free_running_flags	= PEBS_FREERUNNING_FLAGS,

	.large_pebs_flags	= LARGE_PEBS_FLAGS,

	/*

	 * Intel PMCs cannot be accessed sanely above 32 bit width,

	 * so we install an artificial 1<<31 period regardless of

arch/x86/events/intel/ds.c

+3 −3
Original line number Diff line number Diff line
@@ -935,7 +935,7 @@ void intel_pmu_pebs_add(struct perf_event *event) 
	bool needed_cb = pebs_needs_sched_cb(cpuc);



	cpuc->n_pebs++;

	if (hwc->flags & PERF_X86_EVENT_FREERUNNING)

	if (hwc->flags & PERF_X86_EVENT_LARGE_PEBS)

		cpuc->n_large_pebs++;



	pebs_update_state(needed_cb, cpuc, event->ctx->pmu);
@@ -975,7 +975,7 @@ void intel_pmu_pebs_del(struct perf_event *event) 
	bool needed_cb = pebs_needs_sched_cb(cpuc);



	cpuc->n_pebs--;

	if (hwc->flags & PERF_X86_EVENT_FREERUNNING)

	if (hwc->flags & PERF_X86_EVENT_LARGE_PEBS)

		cpuc->n_large_pebs--;



	pebs_update_state(needed_cb, cpuc, event->ctx->pmu);
@@ -1623,7 +1623,7 @@ void __init intel_ds_init(void) 
			x86_pmu.pebs_record_size =

						sizeof(struct pebs_record_skl);

			x86_pmu.drain_pebs = intel_pmu_drain_pebs_nhm;

			x86_pmu.free_running_flags |= PERF_SAMPLE_TIME;

			x86_pmu.large_pebs_flags |= PERF_SAMPLE_TIME;

			break;



		default:

arch/x86/events/intel/uncore_snbep.c

+18 −14
Original line number Diff line number Diff line
@@ -3343,6 +3343,7 @@ static struct extra_reg skx_uncore_cha_extra_regs[] = { 
	SNBEP_CBO_EVENT_EXTRA_REG(0x9134, 0xffff, 0x4),

	SNBEP_CBO_EVENT_EXTRA_REG(0x35, 0xff, 0x8),

	SNBEP_CBO_EVENT_EXTRA_REG(0x36, 0xff, 0x8),

	SNBEP_CBO_EVENT_EXTRA_REG(0x38, 0xff, 0x3),

	EVENT_EXTRA_END

};
@@ -3562,24 +3563,27 @@ static struct intel_uncore_type *skx_msr_uncores[] = { 
	NULL,

};



/*

 * To determine the number of CHAs, it should read bits 27:0 in the CAPID6

 * register which located at Device 30, Function 3, Offset 0x9C. PCI ID 0x2083.

 */

#define SKX_CAPID6		0x9c

#define SKX_CHA_BIT_MASK	GENMASK(27, 0)



static int skx_count_chabox(void)

{

	struct pci_dev *chabox_dev = NULL;

	int bus, count = 0;

	struct pci_dev *dev = NULL;

	u32 val = 0;



	while (1) {

		chabox_dev = pci_get_device(PCI_VENDOR_ID_INTEL, 0x208d, chabox_dev);

		if (!chabox_dev)

			break;

		if (count == 0)

			bus = chabox_dev->bus->number;

		if (bus != chabox_dev->bus->number)

			break;

		count++;

	}

	dev = pci_get_device(PCI_VENDOR_ID_INTEL, 0x2083, dev);

	if (!dev)

		goto out;



	pci_dev_put(chabox_dev);

	return count;

	pci_read_config_dword(dev, SKX_CAPID6, &val);

	val &= SKX_CHA_BIT_MASK;

out:

	pci_dev_put(dev);

	return hweight32(val);

}



void skx_uncore_cpu_init(void)

arch/x86/events/perf_event.h

+3 −3
Original line number Diff line number Diff line
@@ -69,7 +69,7 @@ struct event_constraint { 
#define PERF_X86_EVENT_RDPMC_ALLOWED	0x0100 /* grant rdpmc permission */

#define PERF_X86_EVENT_EXCL_ACCT	0x0200 /* accounted EXCL event */

#define PERF_X86_EVENT_AUTO_RELOAD	0x0400 /* use PEBS auto-reload */

#define PERF_X86_EVENT_FREERUNNING	0x0800 /* use freerunning PEBS */

#define PERF_X86_EVENT_LARGE_PEBS	0x0800 /* use large PEBS */





struct amd_nb {
@@ -88,7 +88,7 @@ struct amd_nb { 
 * REGS_USER can be handled for events limited to ring 3.

 *

 */

#define PEBS_FREERUNNING_FLAGS \

#define LARGE_PEBS_FLAGS \

	(PERF_SAMPLE_IP | PERF_SAMPLE_TID | PERF_SAMPLE_ADDR | \

	PERF_SAMPLE_ID | PERF_SAMPLE_CPU | PERF_SAMPLE_STREAM_ID | \

	PERF_SAMPLE_DATA_SRC | PERF_SAMPLE_IDENTIFIER | \
@@ -609,7 +609,7 @@ struct x86_pmu { 
	struct event_constraint *pebs_constraints;

	void		(*pebs_aliases)(struct perf_event *event);

	int 		max_pebs_events;

	unsigned long	free_running_flags;

	unsigned long	large_pebs_flags;



	/*

	 * Intel LBR