Commit 70ae034d authored by Andrew Kilroy's avatar Andrew Kilroy Committed by Arnaldo Carvalho de Melo
Browse files

perf vendor events arm64: Categorise the Neoverse V1 counters 



This is so they are categorised in the perf list output.  The pmus all
exist in the armv8-common-and-microarch.json and arm-recommended.json
files, so this commit places them into each category's own file under

  tools/perf/pmu-events/arch/arm64/arm/neoverse-v1

Also add the Neoverse V1 to the arm64 mapfile

Reviewed-by: default avatarJohn Garry <john.garry@huawei.com>
Signed-off-by: default avatarAndrew Kilroy <andrew.kilroy@arm.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Jiri Olsa <jolsa@redhat.com>
Cc: Leo Yan <leo.yan@linaro.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Will Deacon <will@kernel.org>
Cc: linux-arm-kernel@lists.infradead.org
Link: https://lore.kernel.org/r/20211006081106.8649-3-andrew.kilroy@arm.com


Signed-off-by: default avatarArnaldo Carvalho de Melo <acme@redhat.com>
parent e166fc32

tools/perf/pmu-events/arch/arm64/arm/neoverse-v1/branch.json

0 → 100644
+8 −0
Original line number Diff line number Diff line 
[

    {

        "ArchStdEvent": "BR_MIS_PRED"

    },

    {

        "ArchStdEvent": "BR_PRED"

    }

]

tools/perf/pmu-events/arch/arm64/arm/neoverse-v1/bus.json

0 → 100644
+20 −0
Original line number Diff line number Diff line 
[

    {

        "ArchStdEvent": "CPU_CYCLES"

    },

    {

        "ArchStdEvent": "BUS_ACCESS"

    },

    {

        "ArchStdEvent": "BUS_CYCLES"

    },

    {

        "ArchStdEvent": "BUS_ACCESS_RD"

    },

    {

        "ArchStdEvent": "BUS_ACCESS_WR"

    },

    {

        "ArchStdEvent": "CNT_CYCLES"

    }

]

tools/perf/pmu-events/arch/arm64/arm/neoverse-v1/cache.json

0 → 100644
+155 −0
Original line number Diff line number Diff line 
[

    {

        "ArchStdEvent": "L1I_CACHE_REFILL"

    },

    {

        "ArchStdEvent": "L1I_TLB_REFILL"

    },

    {

        "ArchStdEvent": "L1D_CACHE_REFILL"

    },

    {

        "ArchStdEvent": "L1D_CACHE"

    },

    {

        "ArchStdEvent": "L1D_TLB_REFILL"

    },

    {

        "ArchStdEvent": "L1I_CACHE"

    },

    {

        "ArchStdEvent": "L1D_CACHE_WB"

    },

    {

        "ArchStdEvent": "L2D_CACHE"

    },

    {

        "ArchStdEvent": "L2D_CACHE_REFILL"

    },

    {

        "ArchStdEvent": "L2D_CACHE_WB"

    },

    {

        "ArchStdEvent": "L2D_CACHE_ALLOCATE"

    },

    {

        "ArchStdEvent": "L1D_TLB"

    },

    {

        "ArchStdEvent": "L1I_TLB"

    },

    {

        "ArchStdEvent": "L3D_CACHE_ALLOCATE"

    },

    {

        "ArchStdEvent": "L3D_CACHE_REFILL"

    },

    {

        "ArchStdEvent": "L3D_CACHE"

    },

    {

        "ArchStdEvent": "L2D_TLB_REFILL"

    },

    {

        "ArchStdEvent": "L2D_TLB"

    },

    {

        "ArchStdEvent": "DTLB_WALK"

    },

    {

        "ArchStdEvent": "ITLB_WALK"

    },

    {

        "ArchStdEvent": "LL_CACHE_RD"

    },

    {

        "ArchStdEvent": "LL_CACHE_MISS_RD"

    },

    {

        "ArchStdEvent": "L1D_CACHE_LMISS_RD"

    },

    {

        "ArchStdEvent": "L1D_CACHE_RD"

    },

    {

        "ArchStdEvent": "L1D_CACHE_WR"

    },

    {

        "ArchStdEvent": "L1D_CACHE_REFILL_RD"

    },

    {

        "ArchStdEvent": "L1D_CACHE_REFILL_WR"

    },

    {

        "ArchStdEvent": "L1D_CACHE_REFILL_INNER"

    },

    {

        "ArchStdEvent": "L1D_CACHE_REFILL_OUTER"

    },

    {

        "ArchStdEvent": "L1D_CACHE_WB_VICTIM"

    },

    {

        "ArchStdEvent": "L1D_CACHE_WB_CLEAN"

    },

    {

        "ArchStdEvent": "L1D_CACHE_INVAL"

    },

    {

        "ArchStdEvent": "L1D_TLB_REFILL_RD"

    },

    {

        "ArchStdEvent": "L1D_TLB_REFILL_WR"

    },

    {

        "ArchStdEvent": "L1D_TLB_RD"

    },

    {

        "ArchStdEvent": "L1D_TLB_WR"

    },

    {

        "ArchStdEvent": "L2D_CACHE_RD"

    },

    {

        "ArchStdEvent": "L2D_CACHE_WR"

    },

    {

        "ArchStdEvent": "L2D_CACHE_REFILL_RD"

    },

    {

        "ArchStdEvent": "L2D_CACHE_REFILL_WR"

    },

    {

        "ArchStdEvent": "L2D_CACHE_WB_VICTIM"

    },

    {

        "ArchStdEvent": "L2D_CACHE_WB_CLEAN"

    },

    {

        "ArchStdEvent": "L2D_CACHE_INVAL"

    },

    {

        "ArchStdEvent": "L2D_TLB_REFILL_RD"

    },

    {

        "ArchStdEvent": "L2D_TLB_REFILL_WR"

    },

    {

        "ArchStdEvent": "L2D_TLB_RD"

    },

    {

        "ArchStdEvent": "L2D_TLB_WR"

    },

    {

        "ArchStdEvent": "L3D_CACHE_RD"

    },

    {

        "ArchStdEvent": "L1I_CACHE_LMISS"

    },

    {

        "ArchStdEvent": "L2D_CACHE_LMISS_RD"

    },

    {

        "ArchStdEvent": "L3D_CACHE_LMISS_RD"

    }

]

tools/perf/pmu-events/arch/arm64/arm/neoverse-v1/exception.json

0 → 100644
+47 −0
Original line number Diff line number Diff line 
[

    {

        "ArchStdEvent": "EXC_TAKEN"

    },

    {

        "ArchStdEvent": "MEMORY_ERROR"

    },

    {

        "ArchStdEvent": "EXC_UNDEF"

    },

    {

        "ArchStdEvent": "EXC_SVC"

    },

    {

        "ArchStdEvent": "EXC_PABORT"

    },

    {

        "ArchStdEvent": "EXC_DABORT"

    },

    {

        "ArchStdEvent": "EXC_IRQ"

    },

    {

        "ArchStdEvent": "EXC_FIQ"

    },

    {

        "ArchStdEvent": "EXC_SMC"

    },

    {

        "ArchStdEvent": "EXC_HVC"

    },

    {

        "ArchStdEvent": "EXC_TRAP_PABORT"

    },

    {

        "ArchStdEvent": "EXC_TRAP_DABORT"

    },

    {

        "ArchStdEvent": "EXC_TRAP_OTHER"

    },

    {

        "ArchStdEvent": "EXC_TRAP_IRQ"

    },

    {

        "ArchStdEvent": "EXC_TRAP_FIQ"

    }

]

tools/perf/pmu-events/arch/arm64/arm/neoverse-v1/instruction.json

0 → 100644
+89 −0
Original line number Diff line number Diff line 
[

    {

        "ArchStdEvent": "SW_INCR"

    },

    {

        "ArchStdEvent": "INST_RETIRED"

    },

    {

        "ArchStdEvent": "EXC_RETURN"

    },

    {

        "ArchStdEvent": "CID_WRITE_RETIRED"

    },

    {

        "ArchStdEvent": "INST_SPEC"

    },

    {

        "ArchStdEvent": "TTBR_WRITE_RETIRED"

    },

    {

        "ArchStdEvent": "BR_RETIRED"

    },

    {

        "ArchStdEvent": "BR_MIS_PRED_RETIRED"

    },

    {

        "ArchStdEvent": "OP_RETIRED"

    },

    {

        "ArchStdEvent": "OP_SPEC"

    },

    {

        "ArchStdEvent": "LDREX_SPEC"

    },

    {

        "ArchStdEvent": "STREX_PASS_SPEC"

    },

    {

        "ArchStdEvent": "STREX_FAIL_SPEC"

    },

    {

        "ArchStdEvent": "STREX_SPEC"

    },

    {

        "ArchStdEvent": "LD_SPEC"

    },

    {

        "ArchStdEvent": "ST_SPEC"

    },

    {

        "ArchStdEvent": "DP_SPEC"

    },

    {

        "ArchStdEvent": "ASE_SPEC"

    },

    {

        "ArchStdEvent": "VFP_SPEC"

    },

    {

        "ArchStdEvent": "PC_WRITE_SPEC"

    },

    {

        "ArchStdEvent": "CRYPTO_SPEC"

    },

    {

        "ArchStdEvent": "BR_IMMED_SPEC"

    },

    {

        "ArchStdEvent": "BR_RETURN_SPEC"

    },

    {

        "ArchStdEvent": "BR_INDIRECT_SPEC"

    },

    {

        "ArchStdEvent": "ISB_SPEC"

    },

    {

        "ArchStdEvent": "DSB_SPEC"

    },

    {

        "ArchStdEvent": "DMB_SPEC"

    },

    {

        "ArchStdEvent": "RC_LD_SPEC"

    },

    {

        "ArchStdEvent": "RC_ST_SPEC"

    }

]