Commit 716572b0 authored by Andy Lutomirski's avatar Andy Lutomirski Committed by Borislav Petkov
Browse files

selftests/x86/fsgsbase: Fix GS == 1, 2, and 3 tests 



Setting GS to 1, 2, or 3 causes a nonsensical part of the IRET microcode
to change GS back to zero on a return from kernel mode to user mode. The
result is that these tests fail randomly depending on when interrupts
happen. Detect when this happens and let the test pass.

Signed-off-by: default avatarAndy Lutomirski <luto@kernel.org>
Signed-off-by: default avatarBorislav Petkov <bp@suse.de>
Link: https://lkml.kernel.org/r/7567fd44a1d60a9424f25b19a998f12149993b0d.1604346596.git.luto@kernel.org
parent b023fd5f

tools/testing/selftests/x86/fsgsbase.c

+10 −2
Original line number Diff line number Diff line
@@ -392,8 +392,8 @@ static void set_gs_and_switch_to(unsigned long local, 
		local = read_base(GS);



		/*

		 * Signal delivery seems to mess up weird selectors.  Put it

		 * back.

		 * Signal delivery is quite likely to change a selector

		 * of 1, 2, or 3 back to 0 due to IRET being defective.

		 */

		asm volatile ("mov %0, %%gs" : : "rm" (force_sel));

	} else {
@@ -411,6 +411,14 @@ static void set_gs_and_switch_to(unsigned long local, 
	if (base == local && sel_pre_sched == sel_post_sched) {

		printf("[OK]\tGS/BASE remained 0x%hx/0x%lx\n",

		       sel_pre_sched, local);

	} else if (base == local && sel_pre_sched >= 1 && sel_pre_sched <= 3 &&

		   sel_post_sched == 0) {

		/*

		 * IRET is misdesigned and will squash selectors 1, 2, or 3

		 * to zero.  Don't fail the test just because this happened.

		 */

		printf("[OK]\tGS/BASE changed from 0x%hx/0x%lx to 0x%hx/0x%lx because IRET is defective\n",

		       sel_pre_sched, local, sel_post_sched, base);

	} else {

		nerrs++;

		printf("[FAIL]\tGS/BASE changed from 0x%hx/0x%lx to 0x%hx/0x%lx\n",