Commit 7694892a authored by Luca Weiss's avatar Luca Weiss Committed by Bjorn Andersson
Browse files

ARM: dts: qcom: msm8226: Add more SoC bits 



Add nodes for sdhc, uart4, i2c, scm, smem, rpm-requests including
dependencies.

Signed-off-by: default avatarLuca Weiss <luca@z3ntu.xyz>
[bjorn: Moved other nodes before "soc" to keep things alphabetical]
Signed-off-by: default avatarBjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20210911232707.259615-5-luca@z3ntu.xyz
parent 61339f36

arch/arm/boot/dts/qcom-msm8226.dtsi

+255 −8
Original line number Diff line number Diff line
@@ -7,6 +7,7 @@ 


#include <dt-bindings/interrupt-controller/arm-gic.h>

#include <dt-bindings/clock/qcom,gcc-msm8974.h>

#include <dt-bindings/gpio/gpio.h>



/ {

	#address-cells = <1>;
@@ -20,6 +21,70 @@ memory@0 { 
		reg = <0x0 0x0>;

	};



	clocks {

		xo_board: xo_board {

			compatible = "fixed-clock";

			#clock-cells = <0>;

			clock-frequency = <19200000>;

		};



		sleep_clk: sleep_clk {

			compatible = "fixed-clock";

			#clock-cells = <0>;

			clock-frequency = <32768>;

		};

	};



	firmware {

		scm {

			compatible = "qcom,scm-msm8226", "qcom,scm";

			clocks = <&gcc GCC_CE1_CLK>, <&gcc GCC_CE1_AXI_CLK>, <&gcc GCC_CE1_AHB_CLK>;

			clock-names = "core", "bus", "iface";

		};

	};



	tcsr_mutex: hwlock {

		compatible = "qcom,tcsr-mutex";

		syscon = <&tcsr_mutex_block 0 0x80>;



		#hwlock-cells = <1>;

	};



	reserved-memory {

		#address-cells = <1>;

		#size-cells = <1>;

		ranges;



		smem_region: smem@3000000 {

			reg = <0x3000000 0x100000>;

			no-map;

		};

	};



	smd {

		compatible = "qcom,smd";



		rpm {

			interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;

			qcom,ipc = <&apcs 8 0>;

			qcom,smd-edge = <15>;



			rpm_requests: rpm-requests {

				compatible = "qcom,rpm-msm8226";

				qcom,smd-channels = "rpm_requests";

			};

		};

	};



	smem {

		compatible = "qcom,smem";



		memory-region = <&smem_region>;

		qcom,rpm-msg-ram = <&rpm_msg_ram>;



		hwlocks = <&tcsr_mutex 3>;

	};



	soc: soc {

		compatible = "simple-bus";

		#address-cells = <1>;
@@ -34,6 +99,136 @@ intc: interrupt-controller@f9000000 { 
			#interrupt-cells = <3>;

		};



		apcs: syscon@f9011000 {

			compatible = "syscon";

			reg = <0xf9011000 0x1000>;

		};



		sdhc_1: sdhci@f9824900 {

			compatible = "qcom,msm8226-sdhci", "qcom,sdhci-msm-v4";

			reg = <0xf9824900 0x11c>, <0xf9824000 0x800>;

			reg-names = "hc_mem", "core_mem";

			interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;

			interrupt-names = "hc_irq", "pwr_irq";

			clocks = <&gcc GCC_SDCC1_APPS_CLK>,

				 <&gcc GCC_SDCC1_AHB_CLK>,

				 <&xo_board>;

			clock-names = "core", "iface", "xo";

			status = "disabled";

		};



		sdhc_2: sdhci@f98a4900 {

			compatible = "qcom,msm8226-sdhci", "qcom,sdhci-msm-v4";

			reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>;

			reg-names = "hc_mem", "core_mem";

			interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;

			interrupt-names = "hc_irq", "pwr_irq";

			clocks = <&gcc GCC_SDCC2_APPS_CLK>,

				 <&gcc GCC_SDCC2_AHB_CLK>,

				 <&xo_board>;

			clock-names = "core", "iface", "xo";

			status = "disabled";

		};



		sdhc_3: sdhci@f9864900 {

			compatible = "qcom,msm8226-sdhci", "qcom,sdhci-msm-v4";

			reg = <0xf9864900 0x11c>, <0xf9864000 0x800>;

			reg-names = "hc_mem", "core_mem";

			interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;

			interrupt-names = "hc_irq", "pwr_irq";

			clocks = <&gcc GCC_SDCC3_APPS_CLK>,

				 <&gcc GCC_SDCC3_AHB_CLK>,

				 <&xo_board>;

			clock-names = "core", "iface", "xo";

			status = "disabled";

		};



		blsp1_uart3: serial@f991f000 {

			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";

			reg = <0xf991f000 0x1000>;

			interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;

			clock-names = "core", "iface";

			status = "disabled";

		};



		blsp1_uart4: serial@f9920000 {

			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";

			reg = <0xf9920000 0x1000>;

			interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&gcc GCC_BLSP1_UART4_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;

			clock-names = "core", "iface";

			status = "disabled";

		};



		blsp1_i2c1: i2c@f9923000 {

			status = "disabled";

			compatible = "qcom,i2c-qup-v2.1.1";

			reg = <0xf9923000 0x1000>;

			interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;

			clock-names = "core", "iface";

			pinctrl-names = "default";

			pinctrl-0 = <&blsp1_i2c1_pins>;

			#address-cells = <1>;

			#size-cells = <0>;

		};



		blsp1_i2c2: i2c@f9924000 {

			status = "disabled";

			compatible = "qcom,i2c-qup-v2.1.1";

			reg = <0xf9924000 0x1000>;

			interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;

			clock-names = "core", "iface";

			pinctrl-names = "default";

			pinctrl-0 = <&blsp1_i2c2_pins>;

			#address-cells = <1>;

			#size-cells = <0>;

		};



		blsp1_i2c3: i2c@f9925000 {

			status = "disabled";

			compatible = "qcom,i2c-qup-v2.1.1";

			reg = <0xf9925000 0x1000>;

			interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;

			clock-names = "core", "iface";

			pinctrl-names = "default";

			pinctrl-0 = <&blsp1_i2c3_pins>;

			#address-cells = <1>;

			#size-cells = <0>;

		};



		blsp1_i2c4: i2c@f9926000 {

			status = "disabled";

			compatible = "qcom,i2c-qup-v2.1.1";

			reg = <0xf9926000 0x1000>;

			interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;

			clock-names = "core", "iface";

			pinctrl-names = "default";

			pinctrl-0 = <&blsp1_i2c4_pins>;

			#address-cells = <1>;

			#size-cells = <0>;

		};



		blsp1_i2c5: i2c@f9927000 {

			status = "disabled";

			compatible = "qcom,i2c-qup-v2.1.1";

			reg = <0xf9927000 0x1000>;

			interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;

			clock-names = "core", "iface";

			pinctrl-names = "default";

			pinctrl-0 = <&blsp1_i2c5_pins>;

			#address-cells = <1>;

			#size-cells = <0>;

		};



		gcc: clock-controller@fc400000 {

			compatible = "qcom,gcc-msm8226";

			reg = <0xfc400000 0x4000>;
@@ -51,15 +246,41 @@ tlmm: pinctrl@fd510000 { 
			interrupt-controller;

			#interrupt-cells = <2>;

			interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;



			blsp1_i2c1_pins: blsp1-i2c1 {

				pins = "gpio2", "gpio3";

				function = "blsp_i2c1";

				drive-strength = <2>;

				bias-disable;

			};



		blsp1_uart3: serial@f991f000 {

			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";

			reg = <0xf991f000 0x1000>;

			interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;

			clock-names = "core", "iface";

			status = "disabled";

			blsp1_i2c2_pins: blsp1-i2c2 {

				pins = "gpio6", "gpio7";

				function = "blsp_i2c2";

				drive-strength = <2>;

				bias-disable;

			};



			blsp1_i2c3_pins: blsp1-i2c3 {

				pins = "gpio10", "gpio11";

				function = "blsp_i2c3";

				drive-strength = <2>;

				bias-disable;

			};



			blsp1_i2c4_pins: blsp1-i2c4 {

				pins = "gpio14", "gpio15";

				function = "blsp_i2c4";

				drive-strength = <2>;

				bias-disable;

			};



			blsp1_i2c5_pins: blsp1-i2c5 {

				pins = "gpio18", "gpio19";

				function = "blsp_i2c5";

				drive-strength = <2>;

				bias-disable;

			};

		};



		restart@fc4ab000 {
@@ -67,6 +288,22 @@ restart@fc4ab000 { 
			reg = <0xfc4ab000 0x4>;

		};



		spmi_bus: spmi@fc4cf000 {

			compatible = "qcom,spmi-pmic-arb";

			reg-names = "core", "intr", "cnfg";

			reg = <0xfc4cf000 0x1000>,

			      <0xfc4cb000 0x1000>,

			      <0xfc4ca000 0x1000>;

			interrupt-names = "periph_irq";

			interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;

			qcom,ee = <0>;

			qcom,channel = <0>;

			#address-cells = <2>;

			#size-cells = <0>;

			interrupt-controller;

			#interrupt-cells = <4>;

		};



		rng@f9bff000 {

			compatible = "qcom,prng";

			reg = <0xf9bff000 0x200>;
@@ -131,6 +368,16 @@ frame@f9028000 { 
				status = "disabled";

			};

		};



		rpm_msg_ram: memory@fc428000 {

			compatible = "qcom,rpm-msg-ram";

			reg = <0xfc428000 0x4000>;

		};



		tcsr_mutex_block: syscon@fd484000 {

			compatible = "syscon";

			reg = <0xfd484000 0x2000>;

		};

	};



	timer {