Commit 77dacc8f authored by Lee Jones's avatar Lee Jones Committed by Kalle Valo
Browse files

mwifiex: pcie: Move tables to the only place they're used 



Saves on 10's of complains about 'defined but not used' variables.

Fixes the following W=1 kernel build warning(s):

 In file included from drivers/net/wireless/marvell/mwifiex/main.h:57,
 from drivers/net/wireless/marvell/mwifiex/main.c:22:
 drivers/net/wireless/marvell/mwifiex/pcie.h:310:41: warning: ‘mwifiex_pcie8997’ defined but not used [-Wunused-const-variable=]
 310 | static const struct mwifiex_pcie_device mwifiex_pcie8997 = {
 | ^~~~~~~~~~~~~~~~
 drivers/net/wireless/marvell/mwifiex/pcie.h:300:41: warning: ‘mwifiex_pcie8897’ defined but not used [-Wunused-const-variable=]
 300 | static const struct mwifiex_pcie_device mwifiex_pcie8897 = {
 | ^~~~~~~~~~~~~~~~
 drivers/net/wireless/marvell/mwifiex/pcie.h:292:41: warning: ‘mwifiex_pcie8766’ defined but not used [-Wunused-const-variable=]
 292 | static const struct mwifiex_pcie_device mwifiex_pcie8766 = {
 | ^~~~~~~~~~~~~~~~

 NB: Repeats 10's of times - snipped for brevity.

Cc: Amitkumar Karwar <amitkarwar@gmail.com>
Cc: Ganapathi Bhat <ganapathi.bhat@nxp.com>
Cc: Xinming Hu <huxinming820@gmail.com>
Cc: Kalle Valo <kvalo@codeaurora.org>
Cc: "David S. Miller" <davem@davemloft.net>
Cc: Jakub Kicinski <kuba@kernel.org>
Cc: linux-wireless@vger.kernel.org
Cc: netdev@vger.kernel.org
Signed-off-by: default avatarLee Jones <lee.jones@linaro.org>
Signed-off-by: default avatarKalle Valo <kvalo@codeaurora.org>
Link: https://lore.kernel.org/r/20200826093401.1458456-2-lee.jones@linaro.org
parent 765be445

drivers/net/wireless/marvell/mwifiex/pcie.c

+149 −0
Original line number Diff line number Diff line
@@ -33,6 +33,155 @@ 


static struct mwifiex_if_ops pcie_ops;



static const struct mwifiex_pcie_card_reg mwifiex_reg_8766 = {

	.cmd_addr_lo = PCIE_SCRATCH_0_REG,

	.cmd_addr_hi = PCIE_SCRATCH_1_REG,

	.cmd_size = PCIE_SCRATCH_2_REG,

	.fw_status = PCIE_SCRATCH_3_REG,

	.cmdrsp_addr_lo = PCIE_SCRATCH_4_REG,

	.cmdrsp_addr_hi = PCIE_SCRATCH_5_REG,

	.tx_rdptr = PCIE_SCRATCH_6_REG,

	.tx_wrptr = PCIE_SCRATCH_7_REG,

	.rx_rdptr = PCIE_SCRATCH_8_REG,

	.rx_wrptr = PCIE_SCRATCH_9_REG,

	.evt_rdptr = PCIE_SCRATCH_10_REG,

	.evt_wrptr = PCIE_SCRATCH_11_REG,

	.drv_rdy = PCIE_SCRATCH_12_REG,

	.tx_start_ptr = 0,

	.tx_mask = MWIFIEX_TXBD_MASK,

	.tx_wrap_mask = 0,

	.rx_mask = MWIFIEX_RXBD_MASK,

	.rx_wrap_mask = 0,

	.tx_rollover_ind = MWIFIEX_BD_FLAG_ROLLOVER_IND,

	.rx_rollover_ind = MWIFIEX_BD_FLAG_ROLLOVER_IND,

	.evt_rollover_ind = MWIFIEX_BD_FLAG_ROLLOVER_IND,

	.ring_flag_sop = 0,

	.ring_flag_eop = 0,

	.ring_flag_xs_sop = 0,

	.ring_flag_xs_eop = 0,

	.ring_tx_start_ptr = 0,

	.pfu_enabled = 0,

	.sleep_cookie = 1,

	.msix_support = 0,

};



static const struct mwifiex_pcie_card_reg mwifiex_reg_8897 = {

	.cmd_addr_lo = PCIE_SCRATCH_0_REG,

	.cmd_addr_hi = PCIE_SCRATCH_1_REG,

	.cmd_size = PCIE_SCRATCH_2_REG,

	.fw_status = PCIE_SCRATCH_3_REG,

	.cmdrsp_addr_lo = PCIE_SCRATCH_4_REG,

	.cmdrsp_addr_hi = PCIE_SCRATCH_5_REG,

	.tx_rdptr = PCIE_RD_DATA_PTR_Q0_Q1,

	.tx_wrptr = PCIE_WR_DATA_PTR_Q0_Q1,

	.rx_rdptr = PCIE_WR_DATA_PTR_Q0_Q1,

	.rx_wrptr = PCIE_RD_DATA_PTR_Q0_Q1,

	.evt_rdptr = PCIE_SCRATCH_10_REG,

	.evt_wrptr = PCIE_SCRATCH_11_REG,

	.drv_rdy = PCIE_SCRATCH_12_REG,

	.tx_start_ptr = 16,

	.tx_mask = 0x03FF0000,

	.tx_wrap_mask = 0x07FF0000,

	.rx_mask = 0x000003FF,

	.rx_wrap_mask = 0x000007FF,

	.tx_rollover_ind = MWIFIEX_BD_FLAG_TX_ROLLOVER_IND,

	.rx_rollover_ind = MWIFIEX_BD_FLAG_RX_ROLLOVER_IND,

	.evt_rollover_ind = MWIFIEX_BD_FLAG_EVT_ROLLOVER_IND,

	.ring_flag_sop = MWIFIEX_BD_FLAG_SOP,

	.ring_flag_eop = MWIFIEX_BD_FLAG_EOP,

	.ring_flag_xs_sop = MWIFIEX_BD_FLAG_XS_SOP,

	.ring_flag_xs_eop = MWIFIEX_BD_FLAG_XS_EOP,

	.ring_tx_start_ptr = MWIFIEX_BD_FLAG_TX_START_PTR,

	.pfu_enabled = 1,

	.sleep_cookie = 0,

	.fw_dump_ctrl = PCIE_SCRATCH_13_REG,

	.fw_dump_start = PCIE_SCRATCH_14_REG,

	.fw_dump_end = 0xcff,

	.fw_dump_host_ready = 0xee,

	.fw_dump_read_done = 0xfe,

	.msix_support = 0,

};



static const struct mwifiex_pcie_card_reg mwifiex_reg_8997 = {

	.cmd_addr_lo = PCIE_SCRATCH_0_REG,

	.cmd_addr_hi = PCIE_SCRATCH_1_REG,

	.cmd_size = PCIE_SCRATCH_2_REG,

	.fw_status = PCIE_SCRATCH_3_REG,

	.cmdrsp_addr_lo = PCIE_SCRATCH_4_REG,

	.cmdrsp_addr_hi = PCIE_SCRATCH_5_REG,

	.tx_rdptr = 0xC1A4,

	.tx_wrptr = 0xC174,

	.rx_rdptr = 0xC174,

	.rx_wrptr = 0xC1A4,

	.evt_rdptr = PCIE_SCRATCH_10_REG,

	.evt_wrptr = PCIE_SCRATCH_11_REG,

	.drv_rdy = PCIE_SCRATCH_12_REG,

	.tx_start_ptr = 16,

	.tx_mask = 0x0FFF0000,

	.tx_wrap_mask = 0x1FFF0000,

	.rx_mask = 0x00000FFF,

	.rx_wrap_mask = 0x00001FFF,

	.tx_rollover_ind = BIT(28),

	.rx_rollover_ind = BIT(12),

	.evt_rollover_ind = MWIFIEX_BD_FLAG_EVT_ROLLOVER_IND,

	.ring_flag_sop = MWIFIEX_BD_FLAG_SOP,

	.ring_flag_eop = MWIFIEX_BD_FLAG_EOP,

	.ring_flag_xs_sop = MWIFIEX_BD_FLAG_XS_SOP,

	.ring_flag_xs_eop = MWIFIEX_BD_FLAG_XS_EOP,

	.ring_tx_start_ptr = MWIFIEX_BD_FLAG_TX_START_PTR,

	.pfu_enabled = 1,

	.sleep_cookie = 0,

	.fw_dump_ctrl = PCIE_SCRATCH_13_REG,

	.fw_dump_start = PCIE_SCRATCH_14_REG,

	.fw_dump_end = 0xcff,

	.fw_dump_host_ready = 0xcc,

	.fw_dump_read_done = 0xdd,

	.msix_support = 0,

};



static struct memory_type_mapping mem_type_mapping_tbl_w8897[] = {

	{"ITCM", NULL, 0, 0xF0},

	{"DTCM", NULL, 0, 0xF1},

	{"SQRAM", NULL, 0, 0xF2},

	{"IRAM", NULL, 0, 0xF3},

	{"APU", NULL, 0, 0xF4},

	{"CIU", NULL, 0, 0xF5},

	{"ICU", NULL, 0, 0xF6},

	{"MAC", NULL, 0, 0xF7},

};



static struct memory_type_mapping mem_type_mapping_tbl_w8997[] = {

	{"DUMP", NULL, 0, 0xDD},

};



static const struct mwifiex_pcie_device mwifiex_pcie8766 = {

	.reg            = &mwifiex_reg_8766,

	.blksz_fw_dl = MWIFIEX_PCIE_BLOCK_SIZE_FW_DNLD,

	.tx_buf_size = MWIFIEX_TX_DATA_BUF_SIZE_2K,

	.can_dump_fw = false,

	.can_ext_scan = true,

};



static const struct mwifiex_pcie_device mwifiex_pcie8897 = {

	.reg            = &mwifiex_reg_8897,

	.blksz_fw_dl = MWIFIEX_PCIE_BLOCK_SIZE_FW_DNLD,

	.tx_buf_size = MWIFIEX_TX_DATA_BUF_SIZE_4K,

	.can_dump_fw = true,

	.mem_type_mapping_tbl = mem_type_mapping_tbl_w8897,

	.num_mem_types = ARRAY_SIZE(mem_type_mapping_tbl_w8897),

	.can_ext_scan = true,

};



static const struct mwifiex_pcie_device mwifiex_pcie8997 = {

	.reg            = &mwifiex_reg_8997,

	.blksz_fw_dl = MWIFIEX_PCIE_BLOCK_SIZE_FW_DNLD,

	.tx_buf_size = MWIFIEX_TX_DATA_BUF_SIZE_4K,

	.can_dump_fw = true,

	.mem_type_mapping_tbl = mem_type_mapping_tbl_w8997,

	.num_mem_types = ARRAY_SIZE(mem_type_mapping_tbl_w8997),

	.can_ext_scan = true,

};



static const struct of_device_id mwifiex_pcie_of_match_table[] = {

	{ .compatible = "pci11ab,2b42" },

	{ .compatible = "pci1b4b,2b42" },

drivers/net/wireless/marvell/mwifiex/pcie.h

+0 −149
Original line number Diff line number Diff line
@@ -158,127 +158,6 @@ struct mwifiex_pcie_card_reg { 
	u8 msix_support;

};



static const struct mwifiex_pcie_card_reg mwifiex_reg_8766 = {

	.cmd_addr_lo = PCIE_SCRATCH_0_REG,

	.cmd_addr_hi = PCIE_SCRATCH_1_REG,

	.cmd_size = PCIE_SCRATCH_2_REG,

	.fw_status = PCIE_SCRATCH_3_REG,

	.cmdrsp_addr_lo = PCIE_SCRATCH_4_REG,

	.cmdrsp_addr_hi = PCIE_SCRATCH_5_REG,

	.tx_rdptr = PCIE_SCRATCH_6_REG,

	.tx_wrptr = PCIE_SCRATCH_7_REG,

	.rx_rdptr = PCIE_SCRATCH_8_REG,

	.rx_wrptr = PCIE_SCRATCH_9_REG,

	.evt_rdptr = PCIE_SCRATCH_10_REG,

	.evt_wrptr = PCIE_SCRATCH_11_REG,

	.drv_rdy = PCIE_SCRATCH_12_REG,

	.tx_start_ptr = 0,

	.tx_mask = MWIFIEX_TXBD_MASK,

	.tx_wrap_mask = 0,

	.rx_mask = MWIFIEX_RXBD_MASK,

	.rx_wrap_mask = 0,

	.tx_rollover_ind = MWIFIEX_BD_FLAG_ROLLOVER_IND,

	.rx_rollover_ind = MWIFIEX_BD_FLAG_ROLLOVER_IND,

	.evt_rollover_ind = MWIFIEX_BD_FLAG_ROLLOVER_IND,

	.ring_flag_sop = 0,

	.ring_flag_eop = 0,

	.ring_flag_xs_sop = 0,

	.ring_flag_xs_eop = 0,

	.ring_tx_start_ptr = 0,

	.pfu_enabled = 0,

	.sleep_cookie = 1,

	.msix_support = 0,

};



static const struct mwifiex_pcie_card_reg mwifiex_reg_8897 = {

	.cmd_addr_lo = PCIE_SCRATCH_0_REG,

	.cmd_addr_hi = PCIE_SCRATCH_1_REG,

	.cmd_size = PCIE_SCRATCH_2_REG,

	.fw_status = PCIE_SCRATCH_3_REG,

	.cmdrsp_addr_lo = PCIE_SCRATCH_4_REG,

	.cmdrsp_addr_hi = PCIE_SCRATCH_5_REG,

	.tx_rdptr = PCIE_RD_DATA_PTR_Q0_Q1,

	.tx_wrptr = PCIE_WR_DATA_PTR_Q0_Q1,

	.rx_rdptr = PCIE_WR_DATA_PTR_Q0_Q1,

	.rx_wrptr = PCIE_RD_DATA_PTR_Q0_Q1,

	.evt_rdptr = PCIE_SCRATCH_10_REG,

	.evt_wrptr = PCIE_SCRATCH_11_REG,

	.drv_rdy = PCIE_SCRATCH_12_REG,

	.tx_start_ptr = 16,

	.tx_mask = 0x03FF0000,

	.tx_wrap_mask = 0x07FF0000,

	.rx_mask = 0x000003FF,

	.rx_wrap_mask = 0x000007FF,

	.tx_rollover_ind = MWIFIEX_BD_FLAG_TX_ROLLOVER_IND,

	.rx_rollover_ind = MWIFIEX_BD_FLAG_RX_ROLLOVER_IND,

	.evt_rollover_ind = MWIFIEX_BD_FLAG_EVT_ROLLOVER_IND,

	.ring_flag_sop = MWIFIEX_BD_FLAG_SOP,

	.ring_flag_eop = MWIFIEX_BD_FLAG_EOP,

	.ring_flag_xs_sop = MWIFIEX_BD_FLAG_XS_SOP,

	.ring_flag_xs_eop = MWIFIEX_BD_FLAG_XS_EOP,

	.ring_tx_start_ptr = MWIFIEX_BD_FLAG_TX_START_PTR,

	.pfu_enabled = 1,

	.sleep_cookie = 0,

	.fw_dump_ctrl = PCIE_SCRATCH_13_REG,

	.fw_dump_start = PCIE_SCRATCH_14_REG,

	.fw_dump_end = 0xcff,

	.fw_dump_host_ready = 0xee,

	.fw_dump_read_done = 0xfe,

	.msix_support = 0,

};



static const struct mwifiex_pcie_card_reg mwifiex_reg_8997 = {

	.cmd_addr_lo = PCIE_SCRATCH_0_REG,

	.cmd_addr_hi = PCIE_SCRATCH_1_REG,

	.cmd_size = PCIE_SCRATCH_2_REG,

	.fw_status = PCIE_SCRATCH_3_REG,

	.cmdrsp_addr_lo = PCIE_SCRATCH_4_REG,

	.cmdrsp_addr_hi = PCIE_SCRATCH_5_REG,

	.tx_rdptr = 0xC1A4,

	.tx_wrptr = 0xC174,

	.rx_rdptr = 0xC174,

	.rx_wrptr = 0xC1A4,

	.evt_rdptr = PCIE_SCRATCH_10_REG,

	.evt_wrptr = PCIE_SCRATCH_11_REG,

	.drv_rdy = PCIE_SCRATCH_12_REG,

	.tx_start_ptr = 16,

	.tx_mask = 0x0FFF0000,

	.tx_wrap_mask = 0x1FFF0000,

	.rx_mask = 0x00000FFF,

	.rx_wrap_mask = 0x00001FFF,

	.tx_rollover_ind = BIT(28),

	.rx_rollover_ind = BIT(12),

	.evt_rollover_ind = MWIFIEX_BD_FLAG_EVT_ROLLOVER_IND,

	.ring_flag_sop = MWIFIEX_BD_FLAG_SOP,

	.ring_flag_eop = MWIFIEX_BD_FLAG_EOP,

	.ring_flag_xs_sop = MWIFIEX_BD_FLAG_XS_SOP,

	.ring_flag_xs_eop = MWIFIEX_BD_FLAG_XS_EOP,

	.ring_tx_start_ptr = MWIFIEX_BD_FLAG_TX_START_PTR,

	.pfu_enabled = 1,

	.sleep_cookie = 0,

	.fw_dump_ctrl = PCIE_SCRATCH_13_REG,

	.fw_dump_start = PCIE_SCRATCH_14_REG,

	.fw_dump_end = 0xcff,

	.fw_dump_host_ready = 0xcc,

	.fw_dump_read_done = 0xdd,

	.msix_support = 0,

};



static struct memory_type_mapping mem_type_mapping_tbl_w8897[] = {

	{"ITCM", NULL, 0, 0xF0},

	{"DTCM", NULL, 0, 0xF1},

	{"SQRAM", NULL, 0, 0xF2},

	{"IRAM", NULL, 0, 0xF3},

	{"APU", NULL, 0, 0xF4},

	{"CIU", NULL, 0, 0xF5},

	{"ICU", NULL, 0, 0xF6},

	{"MAC", NULL, 0, 0xF7},

};



static struct memory_type_mapping mem_type_mapping_tbl_w8997[] = {

	{"DUMP", NULL, 0, 0xDD},

};



struct mwifiex_pcie_device {

	const struct mwifiex_pcie_card_reg *reg;

	u16 blksz_fw_dl;
@@ -289,34 +168,6 @@ struct mwifiex_pcie_device { 
	bool can_ext_scan;

};



static const struct mwifiex_pcie_device mwifiex_pcie8766 = {

	.reg            = &mwifiex_reg_8766,

	.blksz_fw_dl = MWIFIEX_PCIE_BLOCK_SIZE_FW_DNLD,

	.tx_buf_size = MWIFIEX_TX_DATA_BUF_SIZE_2K,

	.can_dump_fw = false,

	.can_ext_scan = true,

};



static const struct mwifiex_pcie_device mwifiex_pcie8897 = {

	.reg            = &mwifiex_reg_8897,

	.blksz_fw_dl = MWIFIEX_PCIE_BLOCK_SIZE_FW_DNLD,

	.tx_buf_size = MWIFIEX_TX_DATA_BUF_SIZE_4K,

	.can_dump_fw = true,

	.mem_type_mapping_tbl = mem_type_mapping_tbl_w8897,

	.num_mem_types = ARRAY_SIZE(mem_type_mapping_tbl_w8897),

	.can_ext_scan = true,

};



static const struct mwifiex_pcie_device mwifiex_pcie8997 = {

	.reg            = &mwifiex_reg_8997,

	.blksz_fw_dl = MWIFIEX_PCIE_BLOCK_SIZE_FW_DNLD,

	.tx_buf_size = MWIFIEX_TX_DATA_BUF_SIZE_4K,

	.can_dump_fw = true,

	.mem_type_mapping_tbl = mem_type_mapping_tbl_w8997,

	.num_mem_types = ARRAY_SIZE(mem_type_mapping_tbl_w8997),

	.can_ext_scan = true,

};



struct mwifiex_evt_buf_desc {

	u64 paddr;

	u16 len;