Commit 787a2b68 authored by Michael Ellerman's avatar Michael Ellerman
Browse files

Merge branch 'topic/ppc-kvm' into next 

Merge our topic branch shared with the kvm-ppc tree.

This brings in one commit that touches the XIVE interrupt controller
logic across core and KVM code.
parents 217ba7dc b1f9be93

arch/powerpc/include/asm/xive-regs.h

+8 −0
Original line number Diff line number Diff line
@@ -37,6 +37,14 @@ 
#define XIVE_ESB_SET_PQ_10	0xe00 /* Load */

#define XIVE_ESB_SET_PQ_11	0xf00 /* Load */



/*

 * Load-after-store ordering

 *

 * Adding this offset to the load address will enforce

 * load-after-store ordering. This is required to use StoreEOI.

 */

#define XIVE_ESB_LD_ST_MO	0x40 /* Load-after-store ordering */



#define XIVE_ESB_VAL_P		0x2

#define XIVE_ESB_VAL_Q		0x1

#define XIVE_ESB_INVALID	0xFF

arch/powerpc/kvm/book3s_hv_rmhandlers.S

+5 −0
Original line number Diff line number Diff line
@@ -2907,6 +2907,11 @@ kvm_cede_exit: 
	beq	4f

	li	r0, 0

	stb	r0, VCPU_CEDED(r9)

	/*

	 * The escalation interrupts are special as we don't EOI them.

	 * There is no need to use the load-after-store ordering offset

	 * to set PQ to 10 as we won't use StoreEOI.

	 */

	li	r6, XIVE_ESB_SET_PQ_10

	b	5f

4:	li	r0, 1

arch/powerpc/kvm/book3s_xive_native.c

+6 −0
Original line number Diff line number Diff line
@@ -31,6 +31,12 @@ static u8 xive_vm_esb_load(struct xive_irq_data *xd, u32 offset) 
{

	u64 val;



	/*

	 * The KVM XIVE native device does not use the XIVE_ESB_SET_PQ_10

	 * load operation, so there is no need to enforce load-after-store

	 * ordering.

	 */



	if (xd->flags & XIVE_IRQ_FLAG_SHIFT_BUG)

		offset |= offset << 4;

arch/powerpc/kvm/book3s_xive_template.c

+3 −0
Original line number Diff line number Diff line
@@ -58,6 +58,9 @@ static u8 GLUE(X_PFX,esb_load)(struct xive_irq_data *xd, u32 offset) 
{

	u64 val;



	if (offset == XIVE_ESB_SET_PQ_10 && xd->flags & XIVE_IRQ_FLAG_STORE_EOI)

		offset |= XIVE_ESB_LD_ST_MO;



	if (xd->flags & XIVE_IRQ_FLAG_SHIFT_BUG)

		offset |= offset << 4;

arch/powerpc/sysdev/xive/common.c

+3 −0
Original line number Diff line number Diff line
@@ -196,6 +196,9 @@ static notrace u8 xive_esb_read(struct xive_irq_data *xd, u32 offset) 
{

	u64 val;



	if (offset == XIVE_ESB_SET_PQ_10 && xd->flags & XIVE_IRQ_FLAG_STORE_EOI)

		offset |= XIVE_ESB_LD_ST_MO;



	/* Handle HW errata */

	if (xd->flags & XIVE_IRQ_FLAG_SHIFT_BUG)

		offset |= offset << 4;