Commit 7969b6ec authored by Rodrigo Siqueira's avatar Rodrigo Siqueira Committed by Alex Deucher
Browse files

drm/amd/display: Remove legacy comments 



To improve the code readability, this commit removes a set of commented
and not used functions for a long time. Notice that now we have the
amdgpu_dm_dtn_log, which prints all the relevant information that we
need.

Signed-off-by: default avatarRodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Reviewed-by: default avatarHarry Wentland <Harry.Wentland@amd.com>
Acked-by: default avatarStylon Wang <stylon.wang@amd.com>
Tested-by: default avatarDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 23344703

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

+0 −160
Original line number Diff line number Diff line
@@ -2199,129 +2199,6 @@ void dcn10_enable_per_frame_crtc_position_reset( 
	DC_SYNC_INFO("Multi-display sync is complete\n");

}



/*static void print_rq_dlg_ttu(

		struct dc *dc,

		struct pipe_ctx *pipe_ctx)

{

	DC_LOG_BANDWIDTH_CALCS(dc->ctx->logger,

			"\n============== DML TTU Output parameters [%d] ==============\n"

			"qos_level_low_wm: %d, \n"

			"qos_level_high_wm: %d, \n"

			"min_ttu_vblank: %d, \n"

			"qos_level_flip: %d, \n"

			"refcyc_per_req_delivery_l: %d, \n"

			"qos_level_fixed_l: %d, \n"

			"qos_ramp_disable_l: %d, \n"

			"refcyc_per_req_delivery_pre_l: %d, \n"

			"refcyc_per_req_delivery_c: %d, \n"

			"qos_level_fixed_c: %d, \n"

			"qos_ramp_disable_c: %d, \n"

			"refcyc_per_req_delivery_pre_c: %d\n"

			"=============================================================\n",

			pipe_ctx->pipe_idx,

			pipe_ctx->ttu_regs.qos_level_low_wm,

			pipe_ctx->ttu_regs.qos_level_high_wm,

			pipe_ctx->ttu_regs.min_ttu_vblank,

			pipe_ctx->ttu_regs.qos_level_flip,

			pipe_ctx->ttu_regs.refcyc_per_req_delivery_l,

			pipe_ctx->ttu_regs.qos_level_fixed_l,

			pipe_ctx->ttu_regs.qos_ramp_disable_l,

			pipe_ctx->ttu_regs.refcyc_per_req_delivery_pre_l,

			pipe_ctx->ttu_regs.refcyc_per_req_delivery_c,

			pipe_ctx->ttu_regs.qos_level_fixed_c,

			pipe_ctx->ttu_regs.qos_ramp_disable_c,

			pipe_ctx->ttu_regs.refcyc_per_req_delivery_pre_c

			);



	DC_LOG_BANDWIDTH_CALCS(dc->ctx->logger,

			"\n============== DML DLG Output parameters [%d] ==============\n"

			"refcyc_h_blank_end: %d, \n"

			"dlg_vblank_end: %d, \n"

			"min_dst_y_next_start: %d, \n"

			"refcyc_per_htotal: %d, \n"

			"refcyc_x_after_scaler: %d, \n"

			"dst_y_after_scaler: %d, \n"

			"dst_y_prefetch: %d, \n"

			"dst_y_per_vm_vblank: %d, \n"

			"dst_y_per_row_vblank: %d, \n"

			"ref_freq_to_pix_freq: %d, \n"

			"vratio_prefetch: %d, \n"

			"refcyc_per_pte_group_vblank_l: %d, \n"

			"refcyc_per_meta_chunk_vblank_l: %d, \n"

			"dst_y_per_pte_row_nom_l: %d, \n"

			"refcyc_per_pte_group_nom_l: %d, \n",

			pipe_ctx->pipe_idx,

			pipe_ctx->dlg_regs.refcyc_h_blank_end,

			pipe_ctx->dlg_regs.dlg_vblank_end,

			pipe_ctx->dlg_regs.min_dst_y_next_start,

			pipe_ctx->dlg_regs.refcyc_per_htotal,

			pipe_ctx->dlg_regs.refcyc_x_after_scaler,

			pipe_ctx->dlg_regs.dst_y_after_scaler,

			pipe_ctx->dlg_regs.dst_y_prefetch,

			pipe_ctx->dlg_regs.dst_y_per_vm_vblank,

			pipe_ctx->dlg_regs.dst_y_per_row_vblank,

			pipe_ctx->dlg_regs.ref_freq_to_pix_freq,

			pipe_ctx->dlg_regs.vratio_prefetch,

			pipe_ctx->dlg_regs.refcyc_per_pte_group_vblank_l,

			pipe_ctx->dlg_regs.refcyc_per_meta_chunk_vblank_l,

			pipe_ctx->dlg_regs.dst_y_per_pte_row_nom_l,

			pipe_ctx->dlg_regs.refcyc_per_pte_group_nom_l

			);



	DC_LOG_BANDWIDTH_CALCS(dc->ctx->logger,

			"\ndst_y_per_meta_row_nom_l: %d, \n"

			"refcyc_per_meta_chunk_nom_l: %d, \n"

			"refcyc_per_line_delivery_pre_l: %d, \n"

			"refcyc_per_line_delivery_l: %d, \n"

			"vratio_prefetch_c: %d, \n"

			"refcyc_per_pte_group_vblank_c: %d, \n"

			"refcyc_per_meta_chunk_vblank_c: %d, \n"

			"dst_y_per_pte_row_nom_c: %d, \n"

			"refcyc_per_pte_group_nom_c: %d, \n"

			"dst_y_per_meta_row_nom_c: %d, \n"

			"refcyc_per_meta_chunk_nom_c: %d, \n"

			"refcyc_per_line_delivery_pre_c: %d, \n"

			"refcyc_per_line_delivery_c: %d \n"

			"========================================================\n",

			pipe_ctx->dlg_regs.dst_y_per_meta_row_nom_l,

			pipe_ctx->dlg_regs.refcyc_per_meta_chunk_nom_l,

			pipe_ctx->dlg_regs.refcyc_per_line_delivery_pre_l,

			pipe_ctx->dlg_regs.refcyc_per_line_delivery_l,

			pipe_ctx->dlg_regs.vratio_prefetch_c,

			pipe_ctx->dlg_regs.refcyc_per_pte_group_vblank_c,

			pipe_ctx->dlg_regs.refcyc_per_meta_chunk_vblank_c,

			pipe_ctx->dlg_regs.dst_y_per_pte_row_nom_c,

			pipe_ctx->dlg_regs.refcyc_per_pte_group_nom_c,

			pipe_ctx->dlg_regs.dst_y_per_meta_row_nom_c,

			pipe_ctx->dlg_regs.refcyc_per_meta_chunk_nom_c,

			pipe_ctx->dlg_regs.refcyc_per_line_delivery_pre_c,

			pipe_ctx->dlg_regs.refcyc_per_line_delivery_c

			);



	DC_LOG_BANDWIDTH_CALCS(dc->ctx->logger,

			"\n============== DML RQ Output parameters [%d] ==============\n"

			"chunk_size: %d \n"

			"min_chunk_size: %d \n"

			"meta_chunk_size: %d \n"

			"min_meta_chunk_size: %d \n"

			"dpte_group_size: %d \n"

			"mpte_group_size: %d \n"

			"swath_height: %d \n"

			"pte_row_height_linear: %d \n"

			"========================================================\n",

			pipe_ctx->pipe_idx,

			pipe_ctx->rq_regs.rq_regs_l.chunk_size,

			pipe_ctx->rq_regs.rq_regs_l.min_chunk_size,

			pipe_ctx->rq_regs.rq_regs_l.meta_chunk_size,

			pipe_ctx->rq_regs.rq_regs_l.min_meta_chunk_size,

			pipe_ctx->rq_regs.rq_regs_l.dpte_group_size,

			pipe_ctx->rq_regs.rq_regs_l.mpte_group_size,

			pipe_ctx->rq_regs.rq_regs_l.swath_height,

			pipe_ctx->rq_regs.rq_regs_l.pte_row_height_linear

			);

}

*/



static void mmhub_read_vm_system_aperture_settings(struct dcn10_hubp *hubp1,

		struct vm_system_aperture_param *apt,

		struct dce_hwseq *hws)
@@ -2429,43 +2306,6 @@ static void dcn10_enable_plane( 
			pipe_ctx->stream_res.opp,

			true);



/* TODO: enable/disable in dm as per update type.

	if (plane_state) {

		DC_LOG_DC(dc->ctx->logger,

				"Pipe:%d 0x%x: addr hi:0x%x, "

				"addr low:0x%x, "

				"src: %d, %d, %d,"

				" %d; dst: %d, %d, %d, %d;\n",

				pipe_ctx->pipe_idx,

				plane_state,

				plane_state->address.grph.addr.high_part,

				plane_state->address.grph.addr.low_part,

				plane_state->src_rect.x,

				plane_state->src_rect.y,

				plane_state->src_rect.width,

				plane_state->src_rect.height,

				plane_state->dst_rect.x,

				plane_state->dst_rect.y,

				plane_state->dst_rect.width,

				plane_state->dst_rect.height);



		DC_LOG_DC(dc->ctx->logger,

				"Pipe %d: width, height, x, y         format:%d\n"

				"viewport:%d, %d, %d, %d\n"

				"recout:  %d, %d, %d, %d\n",

				pipe_ctx->pipe_idx,

				plane_state->format,

				pipe_ctx->plane_res.scl_data.viewport.width,

				pipe_ctx->plane_res.scl_data.viewport.height,

				pipe_ctx->plane_res.scl_data.viewport.x,

				pipe_ctx->plane_res.scl_data.viewport.y,

				pipe_ctx->plane_res.scl_data.recout.width,

				pipe_ctx->plane_res.scl_data.recout.height,

				pipe_ctx->plane_res.scl_data.recout.x,

				pipe_ctx->plane_res.scl_data.recout.y);

		print_rq_dlg_ttu(dc, pipe_ctx);

	}

*/

	if (dc->config.gpu_vm_support)

		dcn10_program_pte_vm(hws, pipe_ctx->plane_res.hubp);