Loading drivers/gpu/drm/tegra/dp.c +16 −2 Original line number Diff line number Diff line Loading @@ -5,9 +5,12 @@ */ #include <drm/drm_dp_helper.h> #include <drm/drm_print.h> #include "dp.h" static const u8 drm_dp_edp_revisions[] = { 0x11, 0x12, 0x13, 0x14 }; static void drm_dp_link_caps_reset(struct drm_dp_link_caps *caps) { caps->enhanced_framing = false; Loading Loading @@ -37,6 +40,7 @@ static void drm_dp_link_reset(struct drm_dp_link *link) link->max_lanes = 0; drm_dp_link_caps_reset(&link->caps); link->edp = 0; link->rate = 0; link->lanes = 0; Loading @@ -55,7 +59,7 @@ static void drm_dp_link_reset(struct drm_dp_link *link) */ int drm_dp_link_probe(struct drm_dp_aux *aux, struct drm_dp_link *link) { u8 dpcd[DP_RECEIVER_CAP_SIZE]; u8 dpcd[DP_RECEIVER_CAP_SIZE], value; int err; drm_dp_link_reset(link); Loading @@ -73,9 +77,19 @@ int drm_dp_link_probe(struct drm_dp_aux *aux, struct drm_dp_link *link) link->caps.fast_training = drm_dp_fast_training_cap(dpcd); link->caps.channel_coding = drm_dp_channel_coding_supported(dpcd); if (drm_dp_alternate_scrambler_reset_cap(dpcd)) if (drm_dp_alternate_scrambler_reset_cap(dpcd)) { link->caps.alternate_scrambler_reset = true; err = drm_dp_dpcd_readb(aux, DP_EDP_DPCD_REV, &value); if (err < 0) return err; if (value >= ARRAY_SIZE(drm_dp_edp_revisions)) DRM_ERROR("unsupported eDP version: %02x\n", value); else link->edp = drm_dp_edp_revisions[value]; } link->rate = link->max_rate; link->lanes = link->max_lanes; Loading drivers/gpu/drm/tegra/dp.h +2 −0 Original line number Diff line number Diff line Loading @@ -60,6 +60,7 @@ void drm_dp_link_caps_copy(struct drm_dp_link_caps *dest, * @max_rate: maximum clock rate supported on the link * @max_lanes: maximum number of lanes supported on the link * @caps: capabilities supported on the link (see &drm_dp_link_caps) * @edp: eDP revision (0x11: eDP 1.1, 0x12: eDP 1.2, ...) * @rate: currently configured link rate * @lanes: currently configured number of lanes */ Loading @@ -69,6 +70,7 @@ struct drm_dp_link { unsigned int max_lanes; struct drm_dp_link_caps caps; unsigned char edp; unsigned int rate; unsigned int lanes; Loading Loading
drivers/gpu/drm/tegra/dp.c +16 −2 Original line number Diff line number Diff line Loading @@ -5,9 +5,12 @@ */ #include <drm/drm_dp_helper.h> #include <drm/drm_print.h> #include "dp.h" static const u8 drm_dp_edp_revisions[] = { 0x11, 0x12, 0x13, 0x14 }; static void drm_dp_link_caps_reset(struct drm_dp_link_caps *caps) { caps->enhanced_framing = false; Loading Loading @@ -37,6 +40,7 @@ static void drm_dp_link_reset(struct drm_dp_link *link) link->max_lanes = 0; drm_dp_link_caps_reset(&link->caps); link->edp = 0; link->rate = 0; link->lanes = 0; Loading @@ -55,7 +59,7 @@ static void drm_dp_link_reset(struct drm_dp_link *link) */ int drm_dp_link_probe(struct drm_dp_aux *aux, struct drm_dp_link *link) { u8 dpcd[DP_RECEIVER_CAP_SIZE]; u8 dpcd[DP_RECEIVER_CAP_SIZE], value; int err; drm_dp_link_reset(link); Loading @@ -73,9 +77,19 @@ int drm_dp_link_probe(struct drm_dp_aux *aux, struct drm_dp_link *link) link->caps.fast_training = drm_dp_fast_training_cap(dpcd); link->caps.channel_coding = drm_dp_channel_coding_supported(dpcd); if (drm_dp_alternate_scrambler_reset_cap(dpcd)) if (drm_dp_alternate_scrambler_reset_cap(dpcd)) { link->caps.alternate_scrambler_reset = true; err = drm_dp_dpcd_readb(aux, DP_EDP_DPCD_REV, &value); if (err < 0) return err; if (value >= ARRAY_SIZE(drm_dp_edp_revisions)) DRM_ERROR("unsupported eDP version: %02x\n", value); else link->edp = drm_dp_edp_revisions[value]; } link->rate = link->max_rate; link->lanes = link->max_lanes; Loading
drivers/gpu/drm/tegra/dp.h +2 −0 Original line number Diff line number Diff line Loading @@ -60,6 +60,7 @@ void drm_dp_link_caps_copy(struct drm_dp_link_caps *dest, * @max_rate: maximum clock rate supported on the link * @max_lanes: maximum number of lanes supported on the link * @caps: capabilities supported on the link (see &drm_dp_link_caps) * @edp: eDP revision (0x11: eDP 1.1, 0x12: eDP 1.2, ...) * @rate: currently configured link rate * @lanes: currently configured number of lanes */ Loading @@ -69,6 +70,7 @@ struct drm_dp_link { unsigned int max_lanes; struct drm_dp_link_caps caps; unsigned char edp; unsigned int rate; unsigned int lanes; Loading