Unverified Commit 7d066dc7 authored by Xin Ji's avatar Xin Ji Committed by Robert Foss
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drm/bridge: anx7625: Tune K value for IVO panel



IVO panel require less input video clock variation than video clock
variation in DP CTS spec.

This patch decreases the K value of ANX7625 which will shrink eDP Tx
video clock variation to meet IVO panel's requirement.

Acked-by: default avatarSam Ravnborg <sam@ravnborg.org>
Signed-off-by: default avatarXin Ji <xji@analogixsemi.com>
Signed-off-by: default avatarRobert Foss <robert.foss@linaro.org>
Link: https://patchwork.freedesktop.org/patch/msgid/20210806104407.2208538-1-xji@analogixsemi.com
parent bd03d440
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+21 −3
Original line number Diff line number Diff line
@@ -384,6 +384,25 @@ static int anx7625_odfc_config(struct anx7625_data *ctx,
	return ret;
}

/*
 * The MIPI source video data exist large variation (e.g. 59Hz ~ 61Hz),
 * anx7625 defined K ratio for matching MIPI input video clock and
 * DP output video clock. Increase K value can match bigger video data
 * variation. IVO panel has small variation than DP CTS spec, need
 * decrease the K value.
 */
static int anx7625_set_k_value(struct anx7625_data *ctx)
{
	struct edid *edid = (struct edid *)ctx->slimport_edid_p.edid_raw_data;

	if (edid->mfg_id[0] == IVO_MID0 && edid->mfg_id[1] == IVO_MID1)
		return anx7625_reg_write(ctx, ctx->i2c.rx_p1_client,
					 MIPI_DIGITAL_ADJ_1, 0x3B);

	return anx7625_reg_write(ctx, ctx->i2c.rx_p1_client,
				 MIPI_DIGITAL_ADJ_1, 0x3D);
}

static int anx7625_dsi_video_timing_config(struct anx7625_data *ctx)
{
	struct device *dev = &ctx->client->dev;
@@ -470,9 +489,8 @@ static int anx7625_dsi_video_timing_config(struct anx7625_data *ctx)
			MIPI_PLL_N_NUM_15_8, (n >> 8) & 0xff);
	ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, MIPI_PLL_N_NUM_7_0,
			(n & 0xff));
	/* Diff */
	ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client,
			MIPI_DIGITAL_ADJ_1, 0x3D);

	anx7625_set_k_value(ctx);

	ret |= anx7625_odfc_config(ctx, post_divider - 1);

+3 −1
Original line number Diff line number Diff line
@@ -211,6 +211,8 @@

#define  MIPI_LANE_CTRL_10               0x0F
#define  MIPI_DIGITAL_ADJ_1     0x1B
#define  IVO_MID0               0x26
#define  IVO_MID1               0xCF

#define  MIPI_PLL_M_NUM_23_16   0x1E
#define  MIPI_PLL_M_NUM_15_8    0x1F