Commit 7f0a38f4 authored by Nancy.Lin's avatar Nancy.Lin Committed by Matthias Brugger
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soc: mediatek: mmsys: add reset control for MT8195 vdosys1 



MT8195 vdosys1 has more than 32 reset bits and a different reset base
than other chips. Add the number of reset bits and reset base in mmsys
private data.

Signed-off-by: default avatarNancy.Lin <nancy.lin@mediatek.com>
Reviewed-by: default avatarAngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: default avatarCK Hu <ck.hu@mediatek.com>
Tested-by: default avatarAngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Tested-by: default avatarBo-Chen Chen <rex-bc.chen@mediatek.com>
Link: https://lore.kernel.org/r/20230113104434.28023-10-nancy.lin@mediatek.com


Signed-off-by: default avatarMatthias Brugger <matthias.bgg@gmail.com>
parent 2004f8be

drivers/soc/mediatek/mt8195-mmsys.h

+1 −0
Original line number Diff line number Diff line
@@ -75,6 +75,7 @@ 
#define MT8195_SOUT_DSC_WRAP1_OUT_TO_SINA_VIRTUAL0		(2 << 16)

#define MT8195_SOUT_DSC_WRAP1_OUT_TO_VPP_MERGE			(3 << 16)



#define MT8195_VDO1_SW0_RST_B					0x1d0

#define MT8195_VDO1_MERGE0_ASYNC_CFG_WD				0xe30

#define MT8195_VDO1_HDRBE_ASYNC_CFG_WD				0xe70

#define MT8195_VDO1_HDR_TOP_CFG					0xd00

drivers/soc/mediatek/mtk-mmsys.c

+2 −0
Original line number Diff line number Diff line
@@ -98,6 +98,8 @@ static const struct mtk_mmsys_driver_data mt8195_vdosys1_driver_data = { 
	.clk_driver = "clk-mt8195-vdo1",

	.routes = mmsys_mt8195_vdo1_routing_table,

	.num_routes = ARRAY_SIZE(mmsys_mt8195_vdo1_routing_table),

	.sw0_rst_offset = MT8195_VDO1_SW0_RST_B,

	.num_resets = 64,

};



static const struct mtk_mmsys_driver_data mt8365_mmsys_driver_data = {