Commit 7f663129 authored by Dikshita Agarwal's avatar Dikshita Agarwal Committed by Mauro Carvalho Chehab
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media: venus: hfi: Define additional 6xx registers 



- Add X2 RPMh registers and definitions from the downstream example.
- Add 6xx core power definitions
- Add 6xx AON definitions
- Add 6xx wrapper tz definitions
- Add 6xx wrapper interrupt definitions
- Add 6xx soft interrupt definitions
- Define wrapper LPI register offsets

Signed-off-by: default avatarDikshita Agarwal <dikshita@codeaurora.org>
Co-developed-by: default avatarBryan O'Donoghue <bryan.odonoghue@linaro.org>
Signed-off-by: default avatarBryan O'Donoghue <bryan.odonoghue@linaro.org>
Signed-off-by: default avatarStanimir Varbanov <stanimir.varbanov@linaro.org>
Signed-off-by: default avatarMauro Carvalho Chehab <mchehab+huawei@kernel.org>
parent 3c5e894d

drivers/media/platform/qcom/venus/hfi_venus_io.h

+30 −0
Original line number Diff line number Diff line
@@ -56,10 +56,22 @@ 
#define UC_REGION_ADDR				0x64

#define UC_REGION_SIZE				0x68



#define CPU_CS_H2XSOFTINTEN_V6			0x148



#define CPU_CS_X2RPMH_V6			0x168

#define CPU_CS_X2RPMH_MASK0_BMSK_V6		0x1

#define CPU_CS_X2RPMH_MASK0_SHFT_V6		0x0

#define CPU_CS_X2RPMH_MASK1_BMSK_V6		0x2

#define CPU_CS_X2RPMH_MASK1_SHFT_V6		0x1

#define CPU_CS_X2RPMH_SWOVERRIDE_BMSK_V6	0x4

#define CPU_CS_X2RPMH_SWOVERRIDE_SHFT_V6	0x3



/* Relative to CPU_IC_BASE */

#define CPU_IC_SOFTINT				0x18

#define CPU_IC_SOFTINT_V6			0x150

#define CPU_IC_SOFTINT_H2A_MASK			0x8000

#define CPU_IC_SOFTINT_H2A_SHIFT		0xf

#define CPU_IC_SOFTINT_H2A_SHIFT_V6		0x0



/* Venus wrapper */

#define WRAPPER_BASE_V6				0x000b0000
@@ -88,6 +100,9 @@ 
#define WRAPPER_INTR_MASK_A2HCPU_MASK		0x4

#define WRAPPER_INTR_MASK_A2HCPU_SHIFT		0x2



#define WRAPPER_INTR_STATUS_A2HWD_MASK_V6	0x8

#define WRAPPER_INTR_MASK_A2HWD_BASK_V6		0x8



#define WRAPPER_INTR_CLEAR			0x14

#define WRAPPER_INTR_CLEAR_A2HWD_MASK		0x10

#define WRAPPER_INTR_CLEAR_A2HWD_SHIFT		0x4
@@ -97,6 +112,8 @@ 
#define WRAPPER_POWER_STATUS			0x44

#define WRAPPER_VDEC_VCODEC_POWER_CONTROL	0x48

#define WRAPPER_VENC_VCODEC_POWER_CONTROL	0x4c

#define WRAPPER_DEBUG_BRIDGE_LPI_CONTROL_V6	0x54

#define WRAPPER_DEBUG_BRIDGE_LPI_STATUS_V6	0x58

#define WRAPPER_VDEC_VENC_AHB_BRIDGE_SYNC_RESET	0x64



#define WRAPPER_CPU_CLOCK_CONFIG		0x2000
@@ -125,4 +142,17 @@ 
#define WRAPPER_VCODEC1_MMCC_POWER_STATUS	0x110

#define WRAPPER_VCODEC1_MMCC_POWER_CONTROL	0x114



/* Venus 6xx */

#define WRAPPER_CORE_POWER_STATUS_V6		0x80

#define WRAPPER_CORE_POWER_CONTROL_V6		0x84



/* Wrapper TZ 6xx */

#define WRAPPER_TZ_BASE_V6			0x000c0000

#define WRAPPER_TZ_CPU_STATUS_V6		0x10



/* Venus AON */

#define AON_BASE_V6				0x000e0000

#define AON_WRAPPER_MVP_NOC_LPI_CONTROL		0x00

#define AON_WRAPPER_MVP_NOC_LPI_STATUS		0x04



#endif