Commit 802b8362 authored by Thomas Bogendoerfer's avatar Thomas Bogendoerfer
Browse files

MIPS: Convert R4600_V1_INDEX_ICACHEOP into a config option 



Use a new config option to enable R4600 V1 index I-cacheop workaround
and remove define from different war.h files.

Signed-off-by: default avatarThomas Bogendoerfer <tsbogend@alpha.franken.de>
parent 8c2ede45

arch/mips/Kconfig

+8 −0
Original line number Diff line number Diff line
@@ -638,6 +638,7 @@ config SGI_IP22 
	select SYS_SUPPORTS_32BIT_KERNEL

	select SYS_SUPPORTS_64BIT_KERNEL

	select SYS_SUPPORTS_BIG_ENDIAN

	select WAR_R4600_V1_INDEX_ICACHEOP

	select MIPS_L1_CACHE_SHIFT_7

	help

	  This are the SGI Indy, Challenge S and Indigo2, as well as certain
@@ -2607,6 +2608,13 @@ config MIPS_ASID_BITS_VARIABLE 
config MIPS_CRC_SUPPORT

	bool



# R4600 erratum.  Due to the lack of errata information the exact

# technical details aren't known.  I've experimentally found that disabling

# interrupts during indexed I-cache flushes seems to be sufficient to deal

# with the issue.

config WAR_R4600_V1_INDEX_ICACHEOP

	bool



#

# - Highmem only makes sense for the 32-bit kernel.

# - The current highmem code will only work properly on physically indexed

arch/mips/include/asm/mach-cavium-octeon/war.h

+0 −1
Original line number Diff line number Diff line
@@ -9,7 +9,6 @@ 
#ifndef __ASM_MIPS_MACH_CAVIUM_OCTEON_WAR_H

#define __ASM_MIPS_MACH_CAVIUM_OCTEON_WAR_H



#define R4600_V1_INDEX_ICACHEOP_WAR	0

#define R4600_V1_HIT_CACHEOP_WAR	0

#define R4600_V2_HIT_CACHEOP_WAR	0

#define BCM1250_M3_WAR			0

arch/mips/include/asm/mach-generic/war.h

+0 −1
Original line number Diff line number Diff line
@@ -8,7 +8,6 @@ 
#ifndef __ASM_MACH_GENERIC_WAR_H

#define __ASM_MACH_GENERIC_WAR_H



#define R4600_V1_INDEX_ICACHEOP_WAR	0

#define R4600_V1_HIT_CACHEOP_WAR	0

#define R4600_V2_HIT_CACHEOP_WAR	0

#define BCM1250_M3_WAR			0

arch/mips/include/asm/mach-ip22/war.h

+0 −1
Original line number Diff line number Diff line
@@ -12,7 +12,6 @@ 
 * R4600 CPU modules for the Indy come with both V1.7 and V2.0 processors.

 */



#define R4600_V1_INDEX_ICACHEOP_WAR	1

#define R4600_V1_HIT_CACHEOP_WAR	1

#define R4600_V2_HIT_CACHEOP_WAR	1

#define BCM1250_M3_WAR			0

arch/mips/include/asm/mach-ip27/war.h

+0 −1
Original line number Diff line number Diff line
@@ -8,7 +8,6 @@ 
#ifndef __ASM_MIPS_MACH_IP27_WAR_H

#define __ASM_MIPS_MACH_IP27_WAR_H



#define R4600_V1_INDEX_ICACHEOP_WAR	0

#define R4600_V1_HIT_CACHEOP_WAR	0

#define R4600_V2_HIT_CACHEOP_WAR	0

#define BCM1250_M3_WAR			0