Commit 80676936 authored by Nicholas Kazlauskas's avatar Nicholas Kazlauskas Committed by Alex Deucher
Browse files

drm/amd/display: Add Z8 allow states to z-state support list 



[Why]
Even if we block Z9 based on crossover threshold it's possible to
allow for Z8.

[How]
There's support for this on DCN314, so update the support types to
include a z8 only and z8_z10 only state.

Update the decide_zstate_support function to allow for specifying
these modes based on the Z8 threshold.

DCN31 has z-state disabled, but still update the legacy code to
map z8_only = disallow and z10_z8_only = z10_only to keep the support
the same.

Reviewed-by: default avatarJun Lei <Jun.Lei@amd.com>
Acked-by: default avatarBrian Chang <Brian.Chang@amd.com>
Signed-off-by: default avatarNicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Tested-by: default avatarDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent fa24e116

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.c

+2 −2
Original line number Diff line number Diff line
@@ -333,8 +333,8 @@ void dcn31_smu_set_zstate_support(struct clk_mgr_internal *clk_mgr, enum dcn_zst 
			(support == DCN_ZSTATE_SUPPORT_ALLOW_Z10_ONLY))

		support = DCN_ZSTATE_SUPPORT_DISALLOW;





	if (support == DCN_ZSTATE_SUPPORT_ALLOW_Z10_ONLY)

	if (support == DCN_ZSTATE_SUPPORT_ALLOW_Z10_ONLY ||

	    support == DCN_ZSTATE_SUPPORT_ALLOW_Z8_Z10_ONLY)

		param = 1;

	else

		param = 0;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_smu.c

+10 −2
Original line number Diff line number Diff line
@@ -346,8 +346,6 @@ void dcn314_smu_set_zstate_support(struct clk_mgr_internal *clk_mgr, enum dcn_zs 
	if (!clk_mgr->smu_present)

		return;



	// Arg[15:0] = 8/9/0 for Z8/Z9/disallow -> existing bits

	// Arg[16] = Disallow Z9 -> new bit

	switch (support) {



	case DCN_ZSTATE_SUPPORT_ALLOW:
@@ -366,6 +364,16 @@ void dcn314_smu_set_zstate_support(struct clk_mgr_internal *clk_mgr, enum dcn_zs 
		param = (1 << 10);

		break;



	case DCN_ZSTATE_SUPPORT_ALLOW_Z8_Z10_ONLY:

		msg_id = VBIOSSMC_MSG_AllowZstatesEntry;

		param = (1 << 10) | (1 << 8);

		break;



	case DCN_ZSTATE_SUPPORT_ALLOW_Z8_ONLY:

		msg_id = VBIOSSMC_MSG_AllowZstatesEntry;

		param = (1 << 8);

		break;



	default: //DCN_ZSTATE_SUPPORT_UNKNOWN

		msg_id = VBIOSSMC_MSG_AllowZstatesEntry;

		param = 0;

drivers/gpu/drm/amd/display/dc/dc.h

+2 −0
Original line number Diff line number Diff line
@@ -493,6 +493,8 @@ enum dcn_pwr_state { 
enum dcn_zstate_support_state {

	DCN_ZSTATE_SUPPORT_UNKNOWN,

	DCN_ZSTATE_SUPPORT_ALLOW,

	DCN_ZSTATE_SUPPORT_ALLOW_Z8_ONLY,

	DCN_ZSTATE_SUPPORT_ALLOW_Z8_Z10_ONLY,

	DCN_ZSTATE_SUPPORT_ALLOW_Z10_ONLY,

	DCN_ZSTATE_SUPPORT_DISALLOW,

};

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

+9 −3
Original line number Diff line number Diff line
@@ -949,6 +949,7 @@ static enum dcn_zstate_support_state decide_zstate_support(struct dc *dc, struc 
	int plane_count;

	int i;

	unsigned int optimized_min_dst_y_next_start_us;

	bool allow_z8 = context->bw_ctx.dml.vba.StutterPeriod > 1000.0;



	plane_count = 0;

	optimized_min_dst_y_next_start_us = 0;
@@ -963,6 +964,8 @@ static enum dcn_zstate_support_state decide_zstate_support(struct dc *dc, struc 
	 * 	2. single eDP, on link 0, 1 plane and stutter period > 5ms

	 * Z10 only cases:

	 * 	1. single eDP, on link 0, 1 plane and stutter period >= 5ms

	 * Z8 cases:

	 * 	1. stutter period sufficient

	 * Zstate not allowed cases:

	 * 	1. Everything else

	 */
@@ -990,11 +993,14 @@ static enum dcn_zstate_support_state decide_zstate_support(struct dc *dc, struc 
		if (context->bw_ctx.dml.vba.StutterPeriod > 5000.0 || optimized_min_dst_y_next_start_us > 5000)

			return DCN_ZSTATE_SUPPORT_ALLOW;

		else if (link->psr_settings.psr_version == DC_PSR_VERSION_1 && !link->panel_config.psr.disable_psr)

			return DCN_ZSTATE_SUPPORT_ALLOW_Z10_ONLY;

			return allow_z8 ? DCN_ZSTATE_SUPPORT_ALLOW_Z8_Z10_ONLY : DCN_ZSTATE_SUPPORT_ALLOW_Z10_ONLY;

		else

			return allow_z8 ? DCN_ZSTATE_SUPPORT_ALLOW_Z8_ONLY : DCN_ZSTATE_SUPPORT_DISALLOW;

	} else if (allow_z8) {

		return DCN_ZSTATE_SUPPORT_ALLOW_Z8_ONLY;

	} else {

		return DCN_ZSTATE_SUPPORT_DISALLOW;

	} else

		return DCN_ZSTATE_SUPPORT_DISALLOW;

	}

}



void dcn20_calculate_dlg_params(