Commit 812283cd authored by Soren Brinkmann's avatar Soren Brinkmann Committed by Greg Kroah-Hartman
Browse files

staging: Add Xilinx Clocking Wizard driver 



Add a driver for the Xilinx Clocking Wizard soft IP. The clocking wizard
provides an AXI interface to dynamically reconfigure the clocking
resources of Xilinx FPGAs.

Signed-off-by: default avatarSoren Brinkmann <soren.brinkmann@xilinx.com>
Acked-by: default avatarLaurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent 6232876b

drivers/staging/Kconfig

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@@ -108,4 +108,6 @@ source "drivers/staging/skein/Kconfig" 


source "drivers/staging/unisys/Kconfig"



source "drivers/staging/clocking-wizard/Kconfig"



endif # STAGING

drivers/staging/Makefile

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@@ -46,3 +46,4 @@ obj-$(CONFIG_MTD_SPINAND_MT29F) += mt29f_spinand/ 
obj-$(CONFIG_GS_FPGABOOT)	+= gs_fpgaboot/

obj-$(CONFIG_CRYPTO_SKEIN)	+= skein/

obj-$(CONFIG_UNISYSSPAR)	+= unisys/

obj-$(CONFIG_COMMON_CLK_XLNX_CLKWZRD)	+= clocking-wizard/

drivers/staging/clocking-wizard/Kconfig

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#

# Xilinx Clocking Wizard Driver

#



config COMMON_CLK_XLNX_CLKWZRD

	tristate "Xilinx Clocking Wizard"

	depends on COMMON_CLK && OF

	---help---

	  Support for the Xilinx Clocking Wizard IP core clock generator.

drivers/staging/clocking-wizard/Makefile

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obj-$(CONFIG_COMMON_CLK_XLNX_CLKWZRD)	+= clk-xlnx-clock-wizard.o

drivers/staging/clocking-wizard/TODO

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TODO:

	- support for fractional multiplier

	- support for fractional divider (output 0 only)

	- support for set_rate() operations (may benefit from Stephen Boyd's

	  refactoring of the clk primitives: https://lkml.org/lkml/2014/9/5/766)

	- review arithmetic

	  - overflow after multiplication?

	  - maximize accuracy before divisions



Patches to:

	Greg Kroah-Hartman <gregkh@linuxfoundation.org>

	Sören Brinkmann <soren.brinkmann@xilinx.com>