Unverified Commit 8128bfe3 authored by Arnd Bergmann's avatar Arnd Bergmann
Browse files

Merge tag 'imx-bindings-5.20' of... 

Merge tag 'imx-bindings-5.20' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into arm/dt

i.MX DT bindings update for 5.20:

- Compatibles for new boards: i.MX7 based Toradex Colibri, DH electronics
  i.MX8M Plus DHCOM and PDK2, TQMa8MPxL, Carrier for Toradex i.MX6 Apalis,
  i.MX93 EVK, PHYTEC i.MX8MM based board.
- A series from Abel Vesa (and Viorel Suman) to split fsl,scu.txt bindings
  into multiple subsystem bindings in yaml format.
- Fix 'line too long' warning caused by Toradex Colibri boards.

* tag 'imx-bindings-5.20' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
  dt-bindings: arm: add TQMa8MPxL board
  dt-bindings: firmware: Add fsl,scu yaml file
  dt-bindings: watchdog: Add fsl,scu-wdt yaml file
  dt-bindings: thermal: Add fsl,scu-thermal yaml file
  dt-bindings: rtc: Add fsl,scu-rtc yaml file
  dt-bindings: power: Add fsl,scu-pd yaml file
  dt-bindings: nvmem: Add fsl,scu-ocotp yaml file
  dt-bindings: input: Add fsl,scu-key yaml file
  dt-bindings: pinctrl: imx: Add fsl,scu-iomux yaml file
  dt-bindings: clk: imx: Add fsl,scu-clk yaml file
  bindings: arm: fsl: Add PHYTEC i.MX8MM devicetree bindings
  dt-bindings: arm: fsl: Add carrier for toradex,apalis-imx6q
  dt-bindings: arm: fsl: Decrease the line length
  dt-bindings: arm: Add DH electronics i.MX8M Plus DHCOM and PDK2
  dt-bindings: arm: fsl: add toradex,colibri-imx7s/d/d-emmc-iris/-v2
  dt-bindings: arm: fsl: add imx93 11x11 evk board
  dt-bindings: arm: fsl: correct 1g vs. 1gb in toradex,colibri-imx6ull-*

Link: https://lore.kernel.org/r/20220709082951.15123-3-shawnguo@kernel.org


Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parents bfcfa1bd c03d7ab1

Documentation/devicetree/bindings/arm/freescale/fsl,scu.txt

deleted100644 → 0
+0 −271
Original line number Diff line number Diff line 
NXP i.MX System Controller Firmware (SCFW)

--------------------------------------------------------------------



The System Controller Firmware (SCFW) is a low-level system function

which runs on a dedicated Cortex-M core to provide power, clock, and

resource management. It exists on some i.MX8 processors. e.g. i.MX8QM

(QM, QP), and i.MX8QX (QXP, DX).



The AP communicates with the SC using a multi-ported MU module found

in the LSIO subsystem. The current definition of this MU module provides

5 remote AP connections to the SC to support up to 5 execution environments

(TZ, HV, standard Linux, etc.). The SC side of this MU module interfaces

with the LSIO DSC IP bus. The SC firmware will communicate with this MU

using the MSI bus.



System Controller Device Node:

============================================================



The scu node with the following properties shall be under the /firmware/ node.



Required properties:

-------------------

- compatible:	should be "fsl,imx-scu".

- mbox-names:	should include "tx0", "tx1", "tx2", "tx3",

			       "rx0", "rx1", "rx2", "rx3";

		include "gip3" if want to support general MU interrupt.

- mboxes:	List of phandle of 4 MU channels for tx, 4 MU channels for

		rx, and 1 optional MU channel for general interrupt.

		All MU channels must be in the same MU instance.

		Cross instances are not allowed. The MU instance can only

		be one of LSIO MU0~M4 for imx8qxp and imx8qm. Users need

		to make sure use the one which is not conflict with other

		execution environments. e.g. ATF.

		Note:

		Channel 0 must be "tx0" or "rx0".

		Channel 1 must be "tx1" or "rx1".

		Channel 2 must be "tx2" or "rx2".

		Channel 3 must be "tx3" or "rx3".

		General interrupt rx channel must be "gip3".

		e.g.

		mboxes = <&lsio_mu1 0 0

			  &lsio_mu1 0 1

			  &lsio_mu1 0 2

			  &lsio_mu1 0 3

			  &lsio_mu1 1 0

			  &lsio_mu1 1 1

			  &lsio_mu1 1 2

			  &lsio_mu1 1 3

			  &lsio_mu1 3 3>;

		See Documentation/devicetree/bindings/mailbox/fsl,mu.yaml

		for detailed mailbox binding.



Note: Each mu which supports general interrupt should have an alias correctly

numbered in "aliases" node.

e.g.

aliases {

	mu1 = &lsio_mu1;

};



i.MX SCU Client Device Node:

============================================================



Client nodes are maintained as children of the relevant IMX-SCU device node.



Power domain bindings based on SCU Message Protocol

------------------------------------------------------------



This binding for the SCU power domain providers uses the generic power

domain binding[2].



Required properties:

- compatible:		Should be one of:

			  "fsl,imx8qm-scu-pd",

			  "fsl,imx8qxp-scu-pd"

			followed by "fsl,scu-pd"



- #power-domain-cells:	Must be 1. Contains the Resource ID used by

			SCU commands.

			See detailed Resource ID list from:

			include/dt-bindings/firmware/imx/rsrc.h



Clock bindings based on SCU Message Protocol

------------------------------------------------------------



This binding uses the common clock binding[1].



Required properties:

- compatible:		Should be one of:

			  "fsl,imx8dxl-clk"

			  "fsl,imx8qm-clk"

			  "fsl,imx8qxp-clk"

			followed by "fsl,scu-clk"

- #clock-cells:		Should be 2.

			Contains the Resource and Clock ID value.

- clocks:		List of clock specifiers, must contain an entry for

			each required entry in clock-names

- clock-names:		Should include entries "xtal_32KHz", "xtal_24MHz"



The clock consumer should specify the desired clock by having the clock

ID in its "clocks" phandle cell.



See the full list of clock IDs from:

include/dt-bindings/clock/imx8qxp-clock.h



Pinctrl bindings based on SCU Message Protocol

------------------------------------------------------------



This binding uses the i.MX common pinctrl binding[3].



Required properties:

- compatible:		Should be one of:

			"fsl,imx8qm-iomuxc",

			"fsl,imx8qxp-iomuxc",

			"fsl,imx8dxl-iomuxc".



Required properties for Pinctrl sub nodes:

- fsl,pins:		Each entry consists of 3 integers which represents

			the mux and config setting for one pin. The first 2

			integers <pin_id mux_mode> are specified using a

			PIN_FUNC_ID macro, which can be found in

			<dt-bindings/pinctrl/pads-imx8qm.h>,

			<dt-bindings/pinctrl/pads-imx8qxp.h>,

			<dt-bindings/pinctrl/pads-imx8dxl.h>.

			The last integer CONFIG is the pad setting value like

			pull-up on this pin.



			Please refer to i.MX8QXP Reference Manual for detailed

			CONFIG settings.



[1] Documentation/devicetree/bindings/clock/clock-bindings.txt

[2] Documentation/devicetree/bindings/power/power-domain.yaml

[3] Documentation/devicetree/bindings/pinctrl/fsl,imx-pinctrl.txt



RTC bindings based on SCU Message Protocol

------------------------------------------------------------



Required properties:

- compatible: should be "fsl,imx8qxp-sc-rtc";



OCOTP bindings based on SCU Message Protocol

------------------------------------------------------------

Required properties:

- compatible:		Should be one of:

			"fsl,imx8qm-scu-ocotp",

			"fsl,imx8qxp-scu-ocotp".

- #address-cells:	Must be 1. Contains byte index

- #size-cells:		Must be 1. Contains byte length



Optional Child nodes:



- Data cells of ocotp:

  Detailed bindings are described in bindings/nvmem/nvmem.txt



Watchdog bindings based on SCU Message Protocol

------------------------------------------------------------



Required properties:

- compatible: should be:

              "fsl,imx8qxp-sc-wdt"

              followed by "fsl,imx-sc-wdt";

Optional properties:

- timeout-sec: contains the watchdog timeout in seconds.



SCU key bindings based on SCU Message Protocol

------------------------------------------------------------



Required properties:

- compatible: should be:

              "fsl,imx8qxp-sc-key"

              followed by "fsl,imx-sc-key";

- linux,keycodes: See Documentation/devicetree/bindings/input/input.yaml



Thermal bindings based on SCU Message Protocol

------------------------------------------------------------



Required properties:

- compatible:			Should be :

				  "fsl,imx8qxp-sc-thermal"

				followed by "fsl,imx-sc-thermal";



- #thermal-sensor-cells:	See Documentation/devicetree/bindings/thermal/thermal-sensor.yaml

				for a description.



Example (imx8qxp):

-------------

aliases {

	mu1 = &lsio_mu1;

};



lsio_mu1: mailbox@5d1c0000 {

	...

	#mbox-cells = <2>;

};



firmware {

	scu {

		compatible = "fsl,imx-scu";

		mbox-names = "tx0", "tx1", "tx2", "tx3",

			     "rx0", "rx1", "rx2", "rx3",

			     "gip3";

		mboxes = <&lsio_mu1 0 0

			  &lsio_mu1 0 1

			  &lsio_mu1 0 2

			  &lsio_mu1 0 3

			  &lsio_mu1 1 0

			  &lsio_mu1 1 1

			  &lsio_mu1 1 2

			  &lsio_mu1 1 3

			  &lsio_mu1 3 3>;



		clk: clk {

			compatible = "fsl,imx8qxp-clk", "fsl,scu-clk";

			#clock-cells = <2>;

		};



		iomuxc {

			compatible = "fsl,imx8qxp-iomuxc";



			pinctrl_lpuart0: lpuart0grp {

				fsl,pins = <

					SC_P_UART0_RX_ADMA_UART0_RX	0x06000020

					SC_P_UART0_TX_ADMA_UART0_TX	0x06000020

				>;

			};

			...

		};



		ocotp: imx8qx-ocotp {

			compatible = "fsl,imx8qxp-scu-ocotp";

			#address-cells = <1>;

			#size-cells = <1>;



			fec_mac0: mac@2c4 {

				reg = <0x2c4 8>;

			};

		};



		pd: imx8qx-pd {

			compatible = "fsl,imx8qxp-scu-pd", "fsl,scu-pd";

			#power-domain-cells = <1>;

		};



		rtc: rtc {

			compatible = "fsl,imx8qxp-sc-rtc";

		};



		scu_key: scu-key {

			compatible = "fsl,imx8qxp-sc-key", "fsl,imx-sc-key";

			linux,keycodes = <KEY_POWER>;

		};



		watchdog {

			compatible = "fsl,imx8qxp-sc-wdt", "fsl,imx-sc-wdt";

			timeout-sec = <60>;

		};



		tsens: thermal-sensor {

			compatible = "fsl,imx8qxp-sc-thermal", "fsl,imx-sc-thermal";

			#thermal-sensor-cells = <1>;

		};

	};

};



serial@5a060000 {

	...

	pinctrl-names = "default";

	pinctrl-0 = <&pinctrl_lpuart0>;

	clocks = <&uart0_clk IMX_SC_R_UART_0 IMX_SC_PM_CLK_PER>;

	clock-names = "ipg";

	power-domains = <&pd IMX_SC_R_UART_0>;

};

Documentation/devicetree/bindings/arm/fsl.yaml

+47 −14
Original line number Diff line number Diff line
@@ -321,6 +321,7 @@ properties: 
          - enum:

              - toradex,apalis_imx6q-ixora      # Apalis iMX6Q/D Module on Ixora Carrier Board

              - toradex,apalis_imx6q-ixora-v1.1 # Apalis iMX6Q/D Module on Ixora V1.1 Carrier Board

              - toradex,apalis_imx6q-ixora-v1.2 # Apalis iMX6Q/D Module on Ixora V1.2 Carrier Board

              - toradex,apalis_imx6q-eval       # Apalis iMX6Q/D Module on Apalis Evaluation Board

          - const: toradex,apalis_imx6q

          - const: fsl,imx6q
@@ -670,30 +671,30 @@ properties: 
      - description: i.MX6ULL Boards with Toradex Colibri iMX6ULL Modules

        items:

          - enum:

              - toradex,colibri-imx6ull-aster     # Colibri iMX6ULL Module on Aster Carrier Board

              - toradex,colibri-imx6ull-eval      # Colibri iMX6ULL Module on Colibri Evaluation Board V3

              - toradex,colibri-imx6ull-iris      # Colibri iMX6ULL Module on Iris Carrier Board

              - toradex,colibri-imx6ull-iris-v2   # Colibri iMX6ULL Module on Iris V2 Carrier Board

              - toradex,colibri-imx6ull-aster     # Aster Carrier Board

              - toradex,colibri-imx6ull-eval      # Colibri Evaluation Board V3

              - toradex,colibri-imx6ull-iris      # Iris Carrier Board

              - toradex,colibri-imx6ull-iris-v2   # Iris V2 Carrier Board

          - const: toradex,colibri-imx6ull        # Colibri iMX6ULL Module

          - const: fsl,imx6ull



      - description: i.MX6ULL Boards with Toradex Colibri iMX6ULL 1GB (eMMC) Module

        items:

          - enum:

              - toradex,colibri-imx6ull-emmc-aster     # Colibri iMX6ULL 1G (eMMC) on Aster Carrier Board

              - toradex,colibri-imx6ull-emmc-eval      # Colibri iMX6ULL 1G (eMMC) on Colibri Evaluation B. V3

              - toradex,colibri-imx6ull-emmc-iris      # Colibri iMX6ULL 1G (eMMC) on Iris Carrier Board

              - toradex,colibri-imx6ull-emmc-iris-v2   # Colibri iMX6ULL 1G (eMMC) on Iris V2 Carrier Board

              - toradex,colibri-imx6ull-emmc-aster     # Aster Carrier Board

              - toradex,colibri-imx6ull-emmc-eval      # Colibri Evaluation B. V3

              - toradex,colibri-imx6ull-emmc-iris      # Iris Carrier Board

              - toradex,colibri-imx6ull-emmc-iris-v2   # Iris V2 Carrier Board

          - const: toradex,colibri-imx6ull-emmc        # Colibri iMX6ULL 1GB (eMMC) Module

          - const: fsl,imx6ull



      - description: i.MX6ULL Boards with Toradex Colibri iMX6ULL Wi-Fi / BT Modules

        items:

          - enum:

              - toradex,colibri-imx6ull-wifi-eval     # Colibri iMX6ULL Wi-Fi / BT M. on Colibri Eval. B. V3

              - toradex,colibri-imx6ull-wifi-aster    # Colibri iMX6ULL Wi-Fi / BT M. on Aster Carrier Board

              - toradex,colibri-imx6ull-wifi-iris     # Colibri iMX6ULL Wi-Fi / BT M. on Iris Carrier Board

              - toradex,colibri-imx6ull-wifi-iris-v2  # Colibri iMX6ULL Wi-Fi / BT M. on Iris V2 Carrier Board

              - toradex,colibri-imx6ull-wifi-eval     # Colibri Eval. B. V3

              - toradex,colibri-imx6ull-wifi-aster    # Aster Carrier Board

              - toradex,colibri-imx6ull-wifi-iris     # Iris Carrier Board

              - toradex,colibri-imx6ull-wifi-iris-v2  # Iris V2 Carrier Board

          - const: toradex,colibri-imx6ull-wifi       # Colibri iMX6ULL Wi-Fi / BT Module

          - const: fsl,imx6ull
@@ -738,6 +739,8 @@ properties: 
          - enum:

              - toradex,colibri-imx7s-aster     # Module on Aster Carrier Board

              - toradex,colibri-imx7s-eval-v3   # Module on Colibri Evaluation Board V3

              - toradex,colibri-imx7s-iris      # Module on Iris Carrier Board

              - toradex,colibri-imx7s-iris-v2   # Module on Iris Carrier Board V2

          - const: toradex,colibri-imx7s

          - const: fsl,imx7s
@@ -789,8 +792,10 @@ properties: 
      - description: i.MX7D Boards with Toradex Colibri i.MX7D Module

        items:

          - enum:

              - toradex,colibri-imx7d-aster   # Colibri iMX7D Module on Aster Carrier Board

              - toradex,colibri-imx7d-eval-v3 # Colibri iMX7D Module on Colibri Evaluation Board V3

              - toradex,colibri-imx7d-aster   # Aster Carrier Board

              - toradex,colibri-imx7d-eval-v3 # Colibri Evaluation Board V3

              - toradex,colibri-imx7d-iris    # Iris Carrier Board

              - toradex,colibri-imx7d-iris-v2 # Iris Carrier Board V2

          - const: toradex,colibri-imx7d

          - const: fsl,imx7d
@@ -799,6 +804,8 @@ properties: 
          - enum:

              - toradex,colibri-imx7d-emmc-aster    # Module on Aster Carrier Board

              - toradex,colibri-imx7d-emmc-eval-v3  # Module on Colibri Evaluation Board V3

              - toradex,colibri-imx7d-emmc-iris     # Module on Iris Carrier Board

              - toradex,colibri-imx7d-emmc-iris-v2  # Module on Iris Carrier Board V2

          - const: toradex,colibri-imx7d-emmc

          - const: fsl,imx7d
@@ -865,6 +872,12 @@ properties: 
          - const: toradex,verdin-imx8mm          # Verdin iMX8M Mini Module

          - const: fsl,imx8mm



      - description: PHYTEC phyCORE-i.MX8MM SoM based boards

        items:

          - const: phytec,imx8mm-phyboard-polis-rdk # phyBOARD-Polis RDK

          - const: phytec,imx8mm-phycore-som        # phyCORE-i.MX8MM SoM

          - const: fsl,imx8mm



      - description: Variscite VAR-SOM-MX8MM based boards

        items:

          - const: variscite,var-som-mx8mm-symphony
@@ -914,6 +927,8 @@ properties: 
      - description: i.MX8MP based Boards

        items:

          - enum:

              - dh,imx8mp-dhcom-som       # i.MX8MP DHCOM SoM

              - dh,imx8mp-dhcom-pdk2      # i.MX8MP DHCOM SoM on PDK2 board

              - fsl,imx8mp-evk            # i.MX8MP EVK Board

              - gateworks,imx8mp-gw74xx   # i.MX8MP Gateworks Board

              - toradex,verdin-imx8mp     # Verdin iMX8M Plus Modules
@@ -952,6 +967,18 @@ properties: 
          - const: toradex,verdin-imx8mp          # Verdin iMX8M Plus Module

          - const: fsl,imx8mp



      - description:

          TQMa8MPxL is a series of LGA SOM featuring NXP i.MX8MP system-on-chip

          variants. It is designed to be soldered on different carrier boards.

          All CPU variants use the same device tree hence only one compatible

          is needed. MBa8MPxL mainboard can be used as starterkit or in a boxed

          version as an industrial computing device.

        items:

          - enum:

              - tq,imx8mp-tqma8mpql-mba8mpxl # TQ-Systems GmbH i.MX8MP TQMa8MPQL SOM on MBa8MPxL

          - const: tq,imx8mp-tqma8mpql       # TQ-Systems GmbH i.MX8MP TQMa8MPQL SOM

          - const: fsl,imx8mp



      - description: i.MX8MQ based Boards

        items:

          - enum:
@@ -1020,6 +1047,12 @@ properties: 
              - fsl,imx8ulp-evk           # i.MX8ULP EVK Board

          - const: fsl,imx8ulp



      - description: i.MX93 based Boards

        items:

          - enum:

              - fsl,imx93-11x11-evk       # i.MX93 11x11 EVK Board

          - const: fsl,imx93



      - description:

          Freescale Vybrid Platform Device Tree Bindings

Documentation/devicetree/bindings/clock/fsl,scu-clk.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/clock/fsl,scu-clk.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: i.MX SCU Client Device Node - Clock bindings based on SCU Message Protocol



maintainers:

  - Abel Vesa <abel.vesa@nxp.com>



description: i.MX SCU Client Device Node

  Client nodes are maintained as children of the relevant IMX-SCU device node.

  This binding uses the common clock binding.

  (Documentation/devicetree/bindings/clock/clock-bindings.txt)

  The clock consumer should specify the desired clock by having the clock

  ID in its "clocks" phandle cell. See the full list of clock IDs from

  include/dt-bindings/clock/imx8qxp-clock.h



properties:

  compatible:

    items:

      - enum:

          - fsl,imx8dxl-clk

          - fsl,imx8qm-clk

          - fsl,imx8qxp-clk

      - const: fsl,scu-clk



  '#clock-cells':

    const: 2



required:

  - compatible

  - '#clock-cells'



additionalProperties: false



examples:

  - |

    clock-controller {

        compatible = "fsl,imx8qxp-clk", "fsl,scu-clk";

        #clock-cells = <2>;

    };

Documentation/devicetree/bindings/firmware/fsl,scu.yaml

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+210 −0
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/firmware/fsl,scu.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: NXP i.MX System Controller Firmware (SCFW)



maintainers:

  - Dong Aisheng <aisheng.dong@nxp.com>



description:

  The System Controller Firmware (SCFW) is a low-level system function

  which runs on a dedicated Cortex-M core to provide power, clock, and

  resource management. It exists on some i.MX8 processors. e.g. i.MX8QM

  (QM, QP), and i.MX8QX (QXP, DX).

  The AP communicates with the SC using a multi-ported MU module found

  in the LSIO subsystem. The current definition of this MU module provides

  5 remote AP connections to the SC to support up to 5 execution environments

  (TZ, HV, standard Linux, etc.). The SC side of this MU module interfaces

  with the LSIO DSC IP bus. The SC firmware will communicate with this MU

  using the MSI bus.



properties:

  compatible:

    const: fsl,imx-scu



  clock-controller:

    description:

      Clock controller node that provides the clocks controlled by the SCU

    $ref: /schemas/clock/fsl,scu-clk.yaml



  ocotp:

    description:

      OCOTP controller node provided by the SCU

    $ref: /schemas/nvmem/fsl,scu-ocotp.yaml



  keys:

    description:

      Keys provided by the SCU

    $ref: /schemas/input/fsl,scu-key.yaml



  mboxes:

    description:

      A list of phandles of TX MU channels followed by a list of phandles of

      RX MU channels. The list may include at the end one more optional MU

      channel for general interrupt. The number of expected tx and rx

      channels is 1 TX and 1 RX channels if MU instance is "fsl,imx8-mu-scu"

      compatible, 4 TX and 4 RX channels otherwise. All MU channels must be

      within the same MU instance. Cross instances are not allowed. The MU

      instance can only be one of LSIO MU0~M4 for imx8qxp and imx8qm. Users

      need to ensure that one is used that does not conflict with other

      execution environments such as ATF.

    oneOf:

      - items:

          - description: TX0 MU channel

          - description: RX0 MU channel

      - items:

          - description: TX0 MU channel

          - description: RX0 MU channel

          - description: optional MU channel for general interrupt

      - items:

          - description: TX0 MU channel

          - description: TX1 MU channel

          - description: TX2 MU channel

          - description: TX3 MU channel

          - description: RX0 MU channel

          - description: RX1 MU channel

          - description: RX2 MU channel

          - description: RX3 MU channel

      - items:

          - description: TX0 MU channel

          - description: TX1 MU channel

          - description: TX2 MU channel

          - description: TX3 MU channel

          - description: RX0 MU channel

          - description: RX1 MU channel

          - description: RX2 MU channel

          - description: RX3 MU channel

          - description: optional MU channel for general interrupt



  mbox-names:

    oneOf:

      - items:

          - const: tx0

          - const: rx0

      - items:

          - const: tx0

          - const: rx0

          - const: gip3

      - items:

          - const: tx0

          - const: tx1

          - const: tx2

          - const: tx3

          - const: rx0

          - const: rx1

          - const: rx2

          - const: rx3

      - items:

          - const: tx0

          - const: tx1

          - const: tx2

          - const: tx3

          - const: rx0

          - const: rx1

          - const: rx2

          - const: rx3

          - const: gip3



  pinctrl:

    description:

      Pin controller provided by the SCU

    $ref: /schemas/pinctrl/fsl,scu-pinctrl.yaml



  power-controller:

    description:

      Power domains controller node that provides the power domains

      controlled by the SCU

    $ref: /schemas/power/fsl,scu-pd.yaml



  rtc:

    description:

      RTC controller provided by the SCU

    $ref: /schemas/rtc/fsl,scu-rtc.yaml



  thermal-sensor:

    description:

      Thermal sensor provided by the SCU

    $ref: /schemas/thermal/fsl,scu-thermal.yaml



  watchdog:

    description:

      Watchdog controller provided by the SCU

    $ref: /schemas/watchdog/fsl,scu-wdt.yaml



required:

  - compatible

  - mbox-names

  - mboxes



additionalProperties: false



examples:

  - |

    #include <dt-bindings/firmware/imx/rsrc.h>

    #include <dt-bindings/input/input.h>

    #include <dt-bindings/pinctrl/pads-imx8qxp.h>



    firmware {

        system-controller {

            compatible = "fsl,imx-scu";

            mbox-names = "tx0", "tx1", "tx2", "tx3",

                         "rx0", "rx1", "rx2", "rx3",

                         "gip3";

            mboxes = <&lsio_mu1 0 0 &lsio_mu1 0 1 &lsio_mu1 0 2 &lsio_mu1 0 3

                      &lsio_mu1 1 0 &lsio_mu1 1 1 &lsio_mu1 1 2 &lsio_mu1 1 3

                      &lsio_mu1 3 3>;



            clock-controller {

                compatible = "fsl,imx8qxp-clk", "fsl,scu-clk";

                #clock-cells = <2>;

            };



            pinctrl {

                compatible = "fsl,imx8qxp-iomuxc";



                pinctrl_lpuart0: lpuart0grp {

                    fsl,pins = <

                        IMX8QXP_UART0_RX_ADMA_UART0_RX   0x06000020

                        IMX8QXP_UART0_TX_ADMA_UART0_TX   0x06000020

                    >;

                };

            };



            ocotp {

                compatible = "fsl,imx8qxp-scu-ocotp";

                #address-cells = <1>;

                #size-cells = <1>;



                fec_mac0: mac@2c4 {

                    reg = <0x2c4 6>;

                };

            };



            power-controller {

                compatible = "fsl,imx8qxp-scu-pd", "fsl,scu-pd";

                #power-domain-cells = <1>;

            };



            rtc {

                compatible = "fsl,imx8qxp-sc-rtc";

            };



            keys {

                compatible = "fsl,imx8qxp-sc-key", "fsl,imx-sc-key";

                linux,keycodes = <KEY_POWER>;

            };



            watchdog {

                compatible = "fsl,imx8qxp-sc-wdt", "fsl,imx-sc-wdt";

                timeout-sec = <60>;

            };



            thermal-sensor {

                compatible = "fsl,imx8qxp-sc-thermal", "fsl,imx-sc-thermal";

                #thermal-sensor-cells = <1>;

            };

        };

    };

Documentation/devicetree/bindings/input/fsl,scu-key.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/input/fsl,scu-key.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: i.MX SCU Client Device Node - SCU key bindings based on SCU Message Protocol



maintainers:

  - Dong Aisheng <aisheng.dong@nxp.com>



description: i.MX SCU Client Device Node

  Client nodes are maintained as children of the relevant IMX-SCU device node.



allOf:

  - $ref: input.yaml#



properties:

  compatible:

    items:

      - const: fsl,imx8qxp-sc-key

      - const: fsl,imx-sc-key



  linux,keycodes:

    maxItems: 1



required:

  - compatible

  - linux,keycodes



additionalProperties: false



examples:

  - |

    #include <dt-bindings/input/input.h>



    keys {

        compatible = "fsl,imx8qxp-sc-key", "fsl,imx-sc-key";

        linux,keycodes = <KEY_POWER>;

    };