Commit 82a1f42f authored by Lijo Lazar's avatar Lijo Lazar Committed by Alex Deucher
Browse files

drm/amdgpu: Release SDMAv4.4.2 ecc irq properly 



Release ECC irq only if irq is enabled - only when RAS feature is enabled
ECC irq gets enabled.

Signed-off-by: default avatarLijo Lazar <lijo.lazar@amd.com>
Reviewed-by: default avatarHawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent d4a4ff1c

drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c

+10 −6
Original line number Diff line number Diff line
@@ -1434,10 +1434,12 @@ static int sdma_v4_4_2_hw_fini(void *handle) 
		return 0;



	inst_mask = GENMASK(adev->sdma.num_instances - 1, 0);

	if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__SDMA)) {

		for (i = 0; i < adev->sdma.num_instances; i++) {

			amdgpu_irq_put(adev, &adev->sdma.ecc_irq,

				       AMDGPU_SDMA_IRQ_INSTANCE0 + i);

		}

	}



	sdma_v4_4_2_inst_ctx_switch_enable(adev, false, inst_mask);

	sdma_v4_4_2_inst_enable(adev, false, inst_mask);
@@ -2073,10 +2075,12 @@ static int sdma_v4_4_2_xcp_suspend(void *handle, uint32_t inst_mask) 
	uint32_t tmp_mask = inst_mask;

	int i;



	if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__SDMA)) {

		for_each_inst(i, tmp_mask) {

			amdgpu_irq_put(adev, &adev->sdma.ecc_irq,

				       AMDGPU_SDMA_IRQ_INSTANCE0 + i);

		}

	}



	sdma_v4_4_2_inst_ctx_switch_enable(adev, false, inst_mask);

	sdma_v4_4_2_inst_enable(adev, false, inst_mask);