Commit 83856aaa authored by Jonathan Cameron's avatar Jonathan Cameron
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staging: iio: frequency: ad9832: Fix alignment for DMA safety 



____cacheline_aligned is an insufficient guarantee for non-coherent DMA
on platforms with 128 byte cachelines above L1.  Switch to the updated
IIO_DMA_MINALIGN definition.  Whilst here, move the marking to cover
the whole union. That has no functional affect, but makes it slightly
easier to see what is going on.

Signed-off-by: default avatarJonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: default avatarAndy Shevchenko <andy.shevchenko@gmail.com>
Link: https://lore.kernel.org/r/20220813160600.1157169-1-jic23@kernel.org
parent 14a4d22e

drivers/staging/iio/frequency/ad9832.c

+2 −2
Original line number Diff line number Diff line
@@ -112,10 +112,10 @@ struct ad9832_state { 
	 * transfer buffers to live in their own cache lines.

	 */

	union {

		__be16			freq_data[4]____cacheline_aligned;

		__be16			freq_data[4];

		__be16			phase_data[2];

		__be16			data;

	};

	} __aligned(IIO_DMA_MINALIGN);

};



static unsigned long ad9832_calc_freqreg(unsigned long mclk, unsigned long fout)