Commit 838b8633 authored by AngeloGioacchino Del Regno's avatar AngeloGioacchino Del Regno Committed by Stephen Boyd
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clk: mediatek: mt7622: Move infracfg to clk-mt7622-infracfg.c 



The infracfg driver cannot be converted to clk_mtk_simple_probe() as
it registers cpumuxes, which is not supported on the common probing
mechanism: for this reason, move it to its own file.
While at it, also convert it to be a platform driver instead; to do
so, also add a .remove() callback for this driver.

During the conversion, error handling was added to the infracfg
probe function.

Signed-off-by: default avatarAngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: default avatarChen-Yu Tsai <wenst@chromium.org>
Link: https://lore.kernel.org/r/20230306140543.1813621-27-angelogioacchino.delregno@collabora.com


Signed-off-by: default avatarStephen Boyd <sboyd@kernel.org>
parent c50e2ea6

drivers/clk/mediatek/Makefile

+2 −1
Original line number Diff line number Diff line
@@ -46,7 +46,8 @@ obj-$(CONFIG_COMMON_CLK_MT2712_MFGCFG) += clk-mt2712-mfg.o 
obj-$(CONFIG_COMMON_CLK_MT2712_MMSYS) += clk-mt2712-mm.o

obj-$(CONFIG_COMMON_CLK_MT2712_VDECSYS) += clk-mt2712-vdec.o

obj-$(CONFIG_COMMON_CLK_MT2712_VENCSYS) += clk-mt2712-venc.o

obj-$(CONFIG_COMMON_CLK_MT7622) += clk-mt7622-apmixedsys.o clk-mt7622.o

obj-$(CONFIG_COMMON_CLK_MT7622) += clk-mt7622-apmixedsys.o clk-mt7622.o \

				   clk-mt7622-infracfg.o

obj-$(CONFIG_COMMON_CLK_MT7622_ETHSYS) += clk-mt7622-eth.o

obj-$(CONFIG_COMMON_CLK_MT7622_HIFSYS) += clk-mt7622-hif.o

obj-$(CONFIG_COMMON_CLK_MT7622_AUDSYS) += clk-mt7622-aud.o

drivers/clk/mediatek/clk-mt7622-infracfg.c

0 → 100644
+127 −0
Original line number Diff line number Diff line 
// SPDX-License-Identifier: GPL-2.0-only

/*

 * Copyright (c) 2017 MediaTek Inc.

 * Copyright (c) 2023 Collabora, Ltd.

 *               AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>

 */



#include <dt-bindings/clock/mt7622-clk.h>

#include <linux/module.h>

#include <linux/platform_device.h>



#include "clk-cpumux.h"

#include "clk-gate.h"

#include "clk-mtk.h"

#include "reset.h"



#define GATE_INFRA(_id, _name, _parent, _shift)				\

	GATE_MTK(_id, _name, _parent, &infra_cg_regs, _shift, &mtk_clk_gate_ops_setclr)



static const struct mtk_gate_regs infra_cg_regs = {

	.set_ofs = 0x40,

	.clr_ofs = 0x44,

	.sta_ofs = 0x48,

};



static const char * const infra_mux1_parents[] = {

	"clkxtal",

	"armpll",

	"main_core_en",

	"armpll"

};



static const struct mtk_composite cpu_muxes[] = {

	MUX(CLK_INFRA_MUX1_SEL, "infra_mux1_sel", infra_mux1_parents, 0x000, 2, 2),

};



static const struct mtk_gate infra_clks[] = {

	GATE_INFRA(CLK_INFRA_DBGCLK_PD, "infra_dbgclk_pd", "axi_sel", 0),

	GATE_INFRA(CLK_INFRA_TRNG, "trng_ck", "axi_sel", 2),

	GATE_INFRA(CLK_INFRA_AUDIO_PD, "infra_audio_pd", "aud_intbus_sel", 5),

	GATE_INFRA(CLK_INFRA_IRRX_PD, "infra_irrx_pd", "irrx_sel", 16),

	GATE_INFRA(CLK_INFRA_APXGPT_PD, "infra_apxgpt_pd", "f10m_ref_sel", 18),

	GATE_INFRA(CLK_INFRA_PMIC_PD, "infra_pmic_pd", "pmicspi_sel", 22),

};



static u16 infrasys_rst_ofs[] = { 0x30 };



static const struct mtk_clk_rst_desc clk_rst_desc = {

	.version = MTK_RST_SIMPLE,

	.rst_bank_ofs = infrasys_rst_ofs,

	.rst_bank_nr = ARRAY_SIZE(infrasys_rst_ofs),

};



static const struct of_device_id of_match_clk_mt7622_infracfg[] = {

	{ .compatible = "mediatek,mt7622-infracfg" },

	{ /* sentinel */ }

};



static int clk_mt7622_infracfg_probe(struct platform_device *pdev)

{

	struct clk_hw_onecell_data *clk_data;

	struct device_node *node = pdev->dev.of_node;

	void __iomem *base;

	int ret;



	base = devm_platform_ioremap_resource(pdev, 0);

	if (IS_ERR(base))

		return PTR_ERR(base);



	clk_data = mtk_alloc_clk_data(CLK_INFRA_NR_CLK);

	if (!clk_data)

		return -ENOMEM;



	ret = mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc);

	if (ret)

		goto free_clk_data;



	ret = mtk_clk_register_gates(&pdev->dev, node, infra_clks,

				     ARRAY_SIZE(infra_clks), clk_data);

	if (ret)

		goto free_clk_data;



	ret = mtk_clk_register_cpumuxes(&pdev->dev, node, cpu_muxes,

					ARRAY_SIZE(cpu_muxes), clk_data);

	if (ret)

		goto unregister_gates;



	ret = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);

	if (ret)

		goto unregister_cpumuxes;



	return 0;



unregister_cpumuxes:

	mtk_clk_unregister_cpumuxes(cpu_muxes, ARRAY_SIZE(cpu_muxes), clk_data);

unregister_gates:

	mtk_clk_unregister_gates(infra_clks, ARRAY_SIZE(infra_clks), clk_data);

free_clk_data:

	mtk_free_clk_data(clk_data);

	return ret;

}



static int clk_mt7622_infracfg_remove(struct platform_device *pdev)

{

	struct device_node *node = pdev->dev.of_node;

	struct clk_hw_onecell_data *clk_data = platform_get_drvdata(pdev);



	of_clk_del_provider(node);

	mtk_clk_unregister_cpumuxes(cpu_muxes, ARRAY_SIZE(cpu_muxes), clk_data);

	mtk_clk_unregister_gates(infra_clks, ARRAY_SIZE(infra_clks), clk_data);

	mtk_free_clk_data(clk_data);



	return 0;

}



static struct platform_driver clk_mt7622_infracfg_drv = {

	.driver = {

		.name = "clk-mt7622-infracfg",

		.of_match_table = of_match_clk_mt7622_infracfg,

	},

	.probe = clk_mt7622_infracfg_probe,

	.remove = clk_mt7622_infracfg_remove,

};

module_platform_driver(clk_mt7622_infracfg_drv);



MODULE_DESCRIPTION("MediaTek MT7622 infracfg clocks driver");

MODULE_LICENSE("GPL");

drivers/clk/mediatek/clk-mt7622.c

+5 −73
Original line number Diff line number Diff line
@@ -18,9 +18,6 @@ 
#include <dt-bindings/clock/mt7622-clk.h>

#include <linux/clk.h> /* for consumer */



#define GATE_INFRA(_id, _name, _parent, _shift)				\

	GATE_MTK(_id, _name, _parent, &infra_cg_regs, _shift, &mtk_clk_gate_ops_setclr)



#define GATE_TOP0(_id, _name, _parent, _shift)				\

	GATE_MTK(_id, _name, _parent, &top0_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr)
@@ -39,13 +36,6 @@ 


static DEFINE_SPINLOCK(mt7622_clk_lock);



static const char * const infra_mux1_parents[] = {

	"clkxtal",

	"armpll",

	"main_core_en",

	"armpll"

};



static const char * const axi_parents[] = {

	"clkxtal",

	"syspll1_d2",
@@ -225,12 +215,6 @@ static const char * const peribus_ck_parents[] = { 
	"syspll1_d4"

};



static const struct mtk_gate_regs infra_cg_regs = {

	.set_ofs = 0x40,

	.clr_ofs = 0x44,

	.sta_ofs = 0x48,

};



static const struct mtk_gate_regs top0_cg_regs = {

	.set_ofs = 0x120,

	.clr_ofs = 0x120,
@@ -255,15 +239,6 @@ static const struct mtk_gate_regs peri1_cg_regs = { 
	.sta_ofs = 0x1C,

};



static const struct mtk_gate infra_clks[] = {

	GATE_INFRA(CLK_INFRA_DBGCLK_PD, "infra_dbgclk_pd", "axi_sel", 0),

	GATE_INFRA(CLK_INFRA_TRNG, "trng_ck", "axi_sel", 2),

	GATE_INFRA(CLK_INFRA_AUDIO_PD, "infra_audio_pd", "aud_intbus_sel", 5),

	GATE_INFRA(CLK_INFRA_IRRX_PD, "infra_irrx_pd", "irrx_sel", 16),

	GATE_INFRA(CLK_INFRA_APXGPT_PD, "infra_apxgpt_pd", "f10m_ref_sel", 18),

	GATE_INFRA(CLK_INFRA_PMIC_PD, "infra_pmic_pd", "pmicspi_sel", 22),

};



static const struct mtk_fixed_clk top_fixed_clks[] = {

	FIXED_CLK(CLK_TOP_TO_U2_PHY, "to_u2_phy", "clkxtal",

		  31250000),
@@ -408,11 +383,6 @@ static const struct mtk_gate peri_clks[] = { 
	GATE_PERI1(CLK_PERI_IRTX_PD, "peri_irtx_pd", "irtx_sel", 2),

};



static struct mtk_composite infra_muxes[] = {

	MUX(CLK_INFRA_MUX1_SEL, "infra_mux1_sel", infra_mux1_parents,

	    0x000, 2, 2),

};



static struct mtk_composite top_muxes[] = {

	/* CLK_CFG_0 */

	MUX_GATE_FLAGS(CLK_TOP_AXI_SEL, "axi_sel", axi_parents,
@@ -512,22 +482,12 @@ static struct mtk_composite peri_muxes[] = { 
	MUX(CLK_PERIBUS_SEL, "peribus_ck_sel", peribus_ck_parents, 0x05C, 0, 1),

};



static u16 infrasys_rst_ofs[] = { 0x30, };

static u16 pericfg_rst_ofs[] = { 0x0, 0x4, };



static const struct mtk_clk_rst_desc clk_rst_desc[] = {

	/* infrasys */

	{

		.version = MTK_RST_SIMPLE,

		.rst_bank_ofs = infrasys_rst_ofs,

		.rst_bank_nr = ARRAY_SIZE(infrasys_rst_ofs),

	},

	/* pericfg */

	{

static const struct mtk_clk_rst_desc clk_rst_desc = {

	.version = MTK_RST_SIMPLE,

	.rst_bank_ofs = pericfg_rst_ofs,

	.rst_bank_nr = ARRAY_SIZE(pericfg_rst_ofs),

	},

};



static int mtk_topckgen_init(struct platform_device *pdev)
@@ -561,31 +521,6 @@ static int mtk_topckgen_init(struct platform_device *pdev) 
	return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);

}



static int mtk_infrasys_init(struct platform_device *pdev)

{

	struct device_node *node = pdev->dev.of_node;

	struct clk_hw_onecell_data *clk_data;

	int r;



	clk_data = mtk_alloc_clk_data(CLK_INFRA_NR_CLK);



	mtk_clk_register_gates(&pdev->dev, node, infra_clks,

			       ARRAY_SIZE(infra_clks), clk_data);



	mtk_clk_register_cpumuxes(&pdev->dev, node, infra_muxes,

				  ARRAY_SIZE(infra_muxes), clk_data);



	r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get,

				   clk_data);

	if (r)

		return r;



	mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc[0]);



	return 0;

}





static int mtk_pericfg_init(struct platform_device *pdev)

{

	struct clk_hw_onecell_data *clk_data;
@@ -610,16 +545,13 @@ static int mtk_pericfg_init(struct platform_device *pdev) 
	if (r)

		return r;



	mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc[1]);

	mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc);



	return 0;

}



static const struct of_device_id of_match_clk_mt7622[] = {

	{

		.compatible = "mediatek,mt7622-infracfg",

		.data = mtk_infrasys_init,

	}, {

		.compatible = "mediatek,mt7622-topckgen",

		.data = mtk_topckgen_init,

	}, {