Commit 868c2a6c authored by David Wronek's avatar David Wronek Committed by Vinod Koul
Browse files

phy: qcom-qmp-ufs: Add SM7150 support 



Add the tables and constants for init sequences for UFS QMP phy found in
SM7150 SoC.

Signed-off-by: default avatarDavid Wronek <davidwronek@gmail.com>
Signed-off-by: default avatarDanila Tikhonov <danila@jiaxyga.com>
Reviewed-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20230311231733.141806-3-danila@jiaxyga.com


Signed-off-by: default avatarVinod Koul <vkoul@kernel.org>
parent 001c00ef

drivers/phy/qualcomm/phy-qcom-qmp-ufs.c

+61 −0
Original line number Diff line number Diff line
@@ -349,6 +349,36 @@ static const struct qmp_phy_init_tbl sdm845_ufsphy_pcs[] = { 
	QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_MULTI_LANE_CTRL1, 0x02),

};



static const struct qmp_phy_init_tbl sm7150_ufsphy_rx[] = {

	QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_LVL, 0x24),

	QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x0f),

	QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),

	QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40),

	QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),

	QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_TERM_BW, 0x5b),

	QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06),

	QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),

	QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1b),

	QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN_HALF, 0x04),

	QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN_QUARTER, 0x04),

	QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN, 0x04),

	QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5b),

	QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x81),

	QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80),

	QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x59),

};



static const struct qmp_phy_init_tbl sm7150_ufsphy_pcs[] = {

	QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_RX_SIGDET_CTRL2, 0x6f),

	QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0f),

	QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_TX_SMALL_AMP_DRV_LVL, 0x02),

	QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_RX_SYM_RESYNC_CTRL, 0x03),

	QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_TX_MID_TERM_CTRL1, 0x43),

	QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_RX_SIGDET_CTRL1, 0x0f),

	QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_RX_MIN_HIBERN8_TIME, 0xff),

	QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_MULTI_LANE_CTRL1, 0x02),

};



static const struct qmp_phy_init_tbl sm8150_ufsphy_serdes[] = {

	QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0xd9),

	QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x11),
@@ -911,6 +941,34 @@ static const struct qmp_phy_cfg sm6115_ufsphy_cfg = { 
	.no_pcs_sw_reset	= true,

};



static const struct qmp_phy_cfg sm7150_ufsphy_cfg = {

	.lanes			= 1,



	.offsets		= &qmp_ufs_offsets,



	.tbls = {

		.serdes		= sdm845_ufsphy_serdes,

		.serdes_num	= ARRAY_SIZE(sdm845_ufsphy_serdes),

		.tx		= sdm845_ufsphy_tx,

		.tx_num		= ARRAY_SIZE(sdm845_ufsphy_tx),

		.rx		= sm7150_ufsphy_rx,

		.rx_num		= ARRAY_SIZE(sm7150_ufsphy_rx),

		.pcs		= sm7150_ufsphy_pcs,

		.pcs_num	= ARRAY_SIZE(sm7150_ufsphy_pcs),

	},

	.tbls_hs_b = {

		.serdes		= sdm845_ufsphy_hs_b_serdes,

		.serdes_num	= ARRAY_SIZE(sdm845_ufsphy_hs_b_serdes),

	},

	.clk_list		= sdm845_ufs_phy_clk_l,

	.num_clks		= ARRAY_SIZE(sdm845_ufs_phy_clk_l),

	.vreg_list		= qmp_phy_vreg_l,

	.num_vregs		= ARRAY_SIZE(qmp_phy_vreg_l),

	.regs			= ufsphy_v3_regs_layout,



	.no_pcs_sw_reset	= true,

};



static const struct qmp_phy_cfg sm8150_ufsphy_cfg = {

	.lanes			= 2,
@@ -1560,6 +1618,9 @@ static const struct of_device_id qmp_ufs_of_match_table[] = { 
	}, {

		.compatible = "qcom,sm6350-qmp-ufs-phy",

		.data = &sdm845_ufsphy_cfg,

	}, {

		.compatible = "qcom,sm7150-qmp-ufs-phy",

		.data = &sm7150_ufsphy_cfg,

	}, {

		.compatible = "qcom,sm8150-qmp-ufs-phy",

		.data = &sm8150_ufsphy_cfg,