Commit 86c2cfb1 authored by Daniel Machon's avatar Daniel Machon Committed by Vinod Koul
Browse files

phy: sparx5-serdes: add registers required for SD/CMU power down 



Add registers required to configure serdeses and CMUs for initial power
down.

Signed-off-by: default avatarDaniel Machon <daniel.machon@microchip.com>
Link: https://lore.kernel.org/r/20230417180335.2787494-2-daniel.machon@microchip.com


Signed-off-by: default avatarVinod Koul <vkoul@kernel.org>
parent 72a5ce33

drivers/phy/microchip/sparx5_serdes_regs.h

+106 −0
Original line number Diff line number Diff line
@@ -2149,6 +2149,92 @@ enum sparx5_serdes_target { 
#define SD_CMU_CMU_05_CFG_BIAS_TP_SEL_1_0_GET(x)\

	FIELD_GET(SD_CMU_CMU_05_CFG_BIAS_TP_SEL_1_0, x)



/*      SD10G_CMU_TARGET:CMU_GRP_1:CMU_06 */

#define SD_CMU_CMU_06(t) \

	__REG(TARGET_SD_CMU, t, 14, 20, 0, 1, 72, 4, 0, 1, 4)



#define SD_CMU_CMU_06_CFG_DISLOS                 BIT(0)

#define SD_CMU_CMU_06_CFG_DISLOS_SET(x)\

	FIELD_PREP(SD_CMU_CMU_06_CFG_DISLOS, x)

#define SD_CMU_CMU_06_CFG_DISLOS_GET(x)\

	FIELD_GET(SD_CMU_CMU_06_CFG_DISLOS, x)



#define SD_CMU_CMU_06_CFG_DISLOL                 BIT(1)

#define SD_CMU_CMU_06_CFG_DISLOL_SET(x)\

	FIELD_PREP(SD_CMU_CMU_06_CFG_DISLOL, x)

#define SD_CMU_CMU_06_CFG_DISLOL_GET(x)\

	FIELD_GET(SD_CMU_CMU_06_CFG_DISLOL, x)



#define SD_CMU_CMU_06_CFG_DCLOL                  BIT(2)

#define SD_CMU_CMU_06_CFG_DCLOL_SET(x)\

	FIELD_PREP(SD_CMU_CMU_06_CFG_DCLOL, x)

#define SD_CMU_CMU_06_CFG_DCLOL_GET(x)\

	FIELD_GET(SD_CMU_CMU_06_CFG_DCLOL, x)



#define SD_CMU_CMU_06_CFG_FORCE_RX_FILT          BIT(3)

#define SD_CMU_CMU_06_CFG_FORCE_RX_FILT_SET(x)\

	FIELD_PREP(SD_CMU_CMU_06_CFG_FORCE_RX_FILT, x)

#define SD_CMU_CMU_06_CFG_FORCE_RX_FILT_GET(x)\

	FIELD_GET(SD_CMU_CMU_06_CFG_FORCE_RX_FILT, x)



#define SD_CMU_CMU_06_CFG_CTRL_LOGIC_PD          BIT(4)

#define SD_CMU_CMU_06_CFG_CTRL_LOGIC_PD_SET(x)\

	FIELD_PREP(SD_CMU_CMU_06_CFG_CTRL_LOGIC_PD, x)

#define SD_CMU_CMU_06_CFG_CTRL_LOGIC_PD_GET(x)\

	FIELD_GET(SD_CMU_CMU_06_CFG_CTRL_LOGIC_PD, x)



#define SD_CMU_CMU_06_CFG_VCO_PD                 BIT(5)

#define SD_CMU_CMU_06_CFG_VCO_PD_SET(x)\

	FIELD_PREP(SD_CMU_CMU_06_CFG_VCO_PD, x)

#define SD_CMU_CMU_06_CFG_VCO_PD_GET(x)\

	FIELD_GET(SD_CMU_CMU_06_CFG_VCO_PD, x)



#define SD_CMU_CMU_06_CFG_VCO_CAL_RESETN         BIT(6)

#define SD_CMU_CMU_06_CFG_VCO_CAL_RESETN_SET(x)\

	FIELD_PREP(SD_CMU_CMU_06_CFG_VCO_CAL_RESETN, x)

#define SD_CMU_CMU_06_CFG_VCO_CAL_RESETN_GET(x)\

	FIELD_GET(SD_CMU_CMU_06_CFG_VCO_CAL_RESETN, x)



#define SD_CMU_CMU_06_CFG_VCO_CAL_BYP            BIT(7)

#define SD_CMU_CMU_06_CFG_VCO_CAL_BYP_SET(x)\

	FIELD_PREP(SD_CMU_CMU_06_CFG_VCO_CAL_BYP, x)

#define SD_CMU_CMU_06_CFG_VCO_CAL_BYP_GET(x)\

	FIELD_GET(SD_CMU_CMU_06_CFG_VCO_CAL_BYP, x)



/*      SD10G_CMU_TARGET:CMU_GRP_1:CMU_08 */

#define SD_CMU_CMU_08(t) \

	__REG(TARGET_SD_CMU, t, 14, 20, 0, 1, 72, 12, 0, 1, 4)



#define SD_CMU_CMU_08_CFG_VFILT2PAD              BIT(0)

#define SD_CMU_CMU_08_CFG_VFILT2PAD_SET(x)\

	FIELD_PREP(SD_CMU_CMU_08_CFG_VFILT2PAD, x)

#define SD_CMU_CMU_08_CFG_VFILT2PAD_GET(x)\

	FIELD_GET(SD_CMU_CMU_08_CFG_VFILT2PAD, x)



#define SD_CMU_CMU_08_CFG_EN_DUMMY               BIT(1)

#define SD_CMU_CMU_08_CFG_EN_DUMMY_SET(x)\

	FIELD_PREP(SD_CMU_CMU_08_CFG_EN_DUMMY, x)

#define SD_CMU_CMU_08_CFG_EN_DUMMY_GET(x)\

	FIELD_GET(SD_CMU_CMU_08_CFG_EN_DUMMY, x)



#define SD_CMU_CMU_08_CFG_CK_TREE_PD             BIT(2)

#define SD_CMU_CMU_08_CFG_CK_TREE_PD_SET(x)\

	FIELD_PREP(SD_CMU_CMU_08_CFG_CK_TREE_PD, x)

#define SD_CMU_CMU_08_CFG_CK_TREE_PD_GET(x)\

	FIELD_GET(SD_CMU_CMU_08_CFG_CK_TREE_PD, x)



#define SD_CMU_CMU_08_CFG_RST_TREE_PD_MAN        BIT(3)

#define SD_CMU_CMU_08_CFG_RST_TREE_PD_MAN_SET(x)\

	FIELD_PREP(SD_CMU_CMU_08_CFG_RST_TREE_PD_MAN, x)

#define SD_CMU_CMU_08_CFG_RST_TREE_PD_MAN_GET(x)\

	FIELD_GET(SD_CMU_CMU_08_CFG_RST_TREE_PD_MAN, x)



#define SD_CMU_CMU_08_CFG_RST_TREE_PD_MAN_EN     BIT(4)

#define SD_CMU_CMU_08_CFG_RST_TREE_PD_MAN_EN_SET(x)\

	FIELD_PREP(SD_CMU_CMU_08_CFG_RST_TREE_PD_MAN_EN, x)

#define SD_CMU_CMU_08_CFG_RST_TREE_PD_MAN_EN_GET(x)\

	FIELD_GET(SD_CMU_CMU_08_CFG_RST_TREE_PD_MAN_EN, x)



/*      SD10G_CMU_TARGET:CMU_GRP_1:CMU_09 */

#define SD_CMU_CMU_09(t)          __REG(TARGET_SD_CMU, t, 14, 20, 0, 1, 72, 16, 0, 1, 4)
@@ -2443,6 +2529,16 @@ enum sparx5_serdes_target { 
#define SD_LANE_SD_LANE_STAT_DBG_OBS_GET(x)\

	FIELD_GET(SD_LANE_SD_LANE_STAT_DBG_OBS, x)



/*      SD_LANE_TARGET:SD_PWR_CFG:QUIET_MODE_6G */

#define SD_LANE_QUIET_MODE_6G(t) \

	__REG(TARGET_SD_LANE, t, 25, 24, 0, 1, 8, 4, 0, 1, 4)



#define SD_LANE_QUIET_MODE_6G_QUIET_MODE         GENMASK(24, 0)

#define SD_LANE_QUIET_MODE_6G_QUIET_MODE_SET(x)\

	FIELD_PREP(SD_LANE_QUIET_MODE_6G_QUIET_MODE, x)

#define SD_LANE_QUIET_MODE_6G_QUIET_MODE_GET(x)\

	FIELD_GET(SD_LANE_QUIET_MODE_6G_QUIET_MODE, x)



/*      SD_LANE_TARGET:CFG_STAT_FX100:MISC */

#define SD_LANE_MISC(t)           __REG(TARGET_SD_LANE, t, 25, 56, 0, 1, 56, 0, 0, 1, 4)
@@ -2692,4 +2788,14 @@ enum sparx5_serdes_target { 
#define SD_LANE_25G_SD_LANE_STAT_DBG_OBS_GET(x)\

	FIELD_GET(SD_LANE_25G_SD_LANE_STAT_DBG_OBS, x)



/*      SD25G_CFG_TARGET:SD_PWR_CFG:QUIET_MODE_6G */

#define SD_LANE_25G_QUIET_MODE_6G(t) \

	__REG(TARGET_SD_LANE_25G, t, 8, 28, 0, 1, 8, 4, 0, 1, 4)



#define SD_LANE_25G_QUIET_MODE_6G_QUIET_MODE     GENMASK(24, 0)

#define SD_LANE_25G_QUIET_MODE_6G_QUIET_MODE_SET(x)\

	FIELD_PREP(SD_LANE_25G_QUIET_MODE_6G_QUIET_MODE, x)

#define SD_LANE_25G_QUIET_MODE_6G_QUIET_MODE_GET(x)\

	FIELD_GET(SD_LANE_25G_QUIET_MODE_6G_QUIET_MODE, x)



#endif /* _SPARX5_SERDES_REGS_H_ */