Commit 86d11e22 authored by Roger Quadros's avatar Roger Quadros Committed by Vinod Koul
Browse files

phy: ti: phy-j721e-wiz: set PMA_CMN_REFCLK_DIG_DIV based on reflk rate 



For J7200-SR2.0 and AM64 we don't model Common refclock divider as
a clock divider as the divisor rate is fixed based on operating
reference clock frequency. We just program the recommended value
into the register. This simplifies the device tree and implementation
a lot.

Signed-off-by: default avatarRoger Quadros <rogerq@kernel.org>
Link: https://lore.kernel.org/r/20220628122255.24265-8-rogerq@kernel.org


Signed-off-by: default avatarVinod Koul <vkoul@kernel.org>
parent edd473d4

drivers/phy/ti/phy-j721e-wiz.c

+24 −0
Original line number Diff line number Diff line
@@ -24,6 +24,11 @@ 
#include <linux/regmap.h>

#include <linux/reset-controller.h>



#define REF_CLK_19_2MHZ         19200000

#define REF_CLK_25MHZ           25000000

#define REF_CLK_100MHZ          100000000

#define REF_CLK_156_25MHZ       156250000



/* SCM offsets */

#define SERDES_SUP_CTRL		0x4400
@@ -1053,6 +1058,25 @@ static int wiz_clock_init(struct wiz *wiz, struct device_node *node) 
	else

		regmap_field_write(wiz->pma_cmn_refclk_int_mode, 0x3);



	switch (wiz->type) {

	case AM64_WIZ_10G:

	case J7200_WIZ_10G:

		switch (rate) {

		case REF_CLK_100MHZ:

			regmap_field_write(wiz->div_sel_field[CMN_REFCLK_DIG_DIV], 0x2);

			break;

		case REF_CLK_156_25MHZ:

			regmap_field_write(wiz->div_sel_field[CMN_REFCLK_DIG_DIV], 0x3);

			break;

		default:

			regmap_field_write(wiz->div_sel_field[CMN_REFCLK_DIG_DIV], 0);

			break;

		}

		break;

	default:

		break;

	}



	if (wiz->data->pma_cmn_refclk1_int_mode) {

		clk = devm_clk_get(dev, "core_ref1_clk");

		if (IS_ERR(clk)) {