Commit 8759924d authored by Martin K. Petersen's avatar Martin K. Petersen
Browse files

Merge patch series "scsi: hisi_sas: Some misc changes" 

Xiang Chen <chenxiang66@hisilicon.com> says:

This series contains some fixes including:

 - Configure initial value of some registers according to HBA model

 - Change DMA setup lock timeout from 100ms to 2.5s

 - Fix warnings detected by sparse

Link: https://lore.kernel.org/r/1684118481-95908-1-git-send-email-chenxiang66@hisilicon.com


Signed-off-by: default avatarMartin K. Petersen <martin.petersen@oracle.com>
parents aa673800 c0328cc5

drivers/scsi/hisi_sas/hisi_sas_v3_hw.c

+20 −8
Original line number Diff line number Diff line
@@ -30,6 +30,7 @@ 
#define SATA_INITI_D2H_STORE_ADDR_LO	0x60

#define SATA_INITI_D2H_STORE_ADDR_HI	0x64

#define CFG_MAX_TAG			0x68

#define TRANS_LOCK_ICT_TIME		0X70

#define HGC_SAS_TX_OPEN_FAIL_RETRY_CTRL	0x84

#define HGC_SAS_TXFAIL_RETRY_CTRL	0x88

#define HGC_GET_ITV_TIME		0x90
@@ -627,13 +628,15 @@ static void interrupt_enable_v3_hw(struct hisi_hba *hisi_hba) 


static void init_reg_v3_hw(struct hisi_hba *hisi_hba)

{

	struct pci_dev *pdev = hisi_hba->pci_dev;

	int i, j;



	/* Global registers init */

	hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE,

			 (u32)((1ULL << hisi_hba->queue_count) - 1));

	hisi_sas_write32(hisi_hba, SAS_AXI_USER3, 0);

	hisi_sas_write32(hisi_hba, CFG_MAX_TAG, 0xfff0400);

	/* time / CLK_AHB = 2.5s / 2ns = 0x4A817C80 */

	hisi_sas_write32(hisi_hba, TRANS_LOCK_ICT_TIME, 0x4A817C80);

	hisi_sas_write32(hisi_hba, HGC_SAS_TXFAIL_RETRY_CTRL, 0x108);

	hisi_sas_write32(hisi_hba, CFG_AGING_TIME, 0x1);

	hisi_sas_write32(hisi_hba, INT_COAL_EN, 0x1);
@@ -652,6 +655,9 @@ static void init_reg_v3_hw(struct hisi_hba *hisi_hba) 
	hisi_sas_write32(hisi_hba, ARQOS_ARCACHE_CFG, 0xf0f0);

	hisi_sas_write32(hisi_hba, HYPER_STREAM_ID_EN_CFG, 1);



	if (pdev->revision < 0x30)

		hisi_sas_write32(hisi_hba, SAS_AXI_USER3, 0);



	interrupt_enable_v3_hw(hisi_hba);

	for (i = 0; i < hisi_hba->n_phy; i++) {

		enum sas_linkrate max;
@@ -669,7 +675,6 @@ static void init_reg_v3_hw(struct hisi_hba *hisi_hba) 
		prog_phy_link_rate |= hisi_sas_get_prog_phy_linkrate_mask(max);

		hisi_sas_phy_write32(hisi_hba, i, PROG_PHY_LINK_RATE,

			prog_phy_link_rate);

		hisi_sas_phy_write32(hisi_hba, i, SERDES_CFG, 0xffc00);

		hisi_sas_phy_write32(hisi_hba, i, SAS_RX_TRAIN_TIMER, 0x13e80);

		hisi_sas_phy_write32(hisi_hba, i, CHL_INT0, 0xffffffff);

		hisi_sas_phy_write32(hisi_hba, i, CHL_INT1, 0xffffffff);
@@ -680,12 +685,17 @@ static void init_reg_v3_hw(struct hisi_hba *hisi_hba) 
		hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_OOB_RESTART_MSK, 0x1);

		hisi_sas_phy_write32(hisi_hba, i, STP_LINK_TIMER, 0x7f7a120);

		hisi_sas_phy_write32(hisi_hba, i, CON_CFG_DRIVER, 0x2a0a01);

		hisi_sas_phy_write32(hisi_hba, i, SAS_SSP_CON_TIMER_CFG, 0x32);

		hisi_sas_phy_write32(hisi_hba, i, SAS_EC_INT_COAL_TIME,

				     0x30f4240);

		hisi_sas_phy_write32(hisi_hba, i, AIP_LIMIT, 0x2ffff);



		/* set value through firmware for 920B and later version */

		if (pdev->revision < 0x30) {

			hisi_sas_phy_write32(hisi_hba, i, SAS_SSP_CON_TIMER_CFG, 0x32);

			hisi_sas_phy_write32(hisi_hba, i, SERDES_CFG, 0xffc00);

			/* used for 12G negotiate */

			hisi_sas_phy_write32(hisi_hba, i, COARSETUNE_TIME, 0x1e);

		hisi_sas_phy_write32(hisi_hba, i, AIP_LIMIT, 0x2ffff);

		}



		/* get default FFE configuration for BIST */

		for (j = 0; j < FFE_CFG_MAX; j++) {
@@ -2206,6 +2216,7 @@ slot_err_v3_hw(struct hisi_hba *hisi_hba, struct sas_task *task, 
	u32 trans_tx_fail_type = le32_to_cpu(record->trans_tx_fail_type);

	u16 sipc_rx_err_type = le16_to_cpu(record->sipc_rx_err_type);

	u32 dw3 = le32_to_cpu(complete_hdr->dw3);

	u32 dw0 = le32_to_cpu(complete_hdr->dw0);



	switch (task->task_proto) {

	case SAS_PROTOCOL_SSP:
@@ -2215,8 +2226,8 @@ slot_err_v3_hw(struct hisi_hba *hisi_hba, struct sas_task *task, 
			 * but I/O information has been written to the host memory, we examine

			 * response IU.

			 */

			if (!(complete_hdr->dw0 & CMPLT_HDR_RSPNS_GOOD_MSK) &&

				(complete_hdr->dw0 & CMPLT_HDR_RSPNS_XFRD_MSK))

			if (!(dw0 & CMPLT_HDR_RSPNS_GOOD_MSK) &&

			    (dw0 & CMPLT_HDR_RSPNS_XFRD_MSK))

				return false;



			ts->residual = trans_tx_fail_type;
@@ -2232,7 +2243,7 @@ slot_err_v3_hw(struct hisi_hba *hisi_hba, struct sas_task *task, 
	case SAS_PROTOCOL_SATA:

	case SAS_PROTOCOL_STP:

	case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP:

		if ((complete_hdr->dw0 & CMPLT_HDR_RSPNS_XFRD_MSK) &&

		if ((dw0 & CMPLT_HDR_RSPNS_XFRD_MSK) &&

		    (sipc_rx_err_type & RX_FIS_STATUS_ERR_MSK)) {

			ts->stat = SAS_PROTO_RESPONSE;

		} else if (dma_rx_err_type & RX_DATA_LEN_UNDERFLOW_MSK) {
@@ -2999,6 +3010,7 @@ static const struct hisi_sas_debugfs_reg_lu debugfs_global_reg_lu[] = { 
	HISI_SAS_DEBUGFS_REG(SATA_INITI_D2H_STORE_ADDR_LO),

	HISI_SAS_DEBUGFS_REG(SATA_INITI_D2H_STORE_ADDR_HI),

	HISI_SAS_DEBUGFS_REG(CFG_MAX_TAG),

	HISI_SAS_DEBUGFS_REG(TRANS_LOCK_ICT_TIME),

	HISI_SAS_DEBUGFS_REG(HGC_SAS_TX_OPEN_FAIL_RETRY_CTRL),

	HISI_SAS_DEBUGFS_REG(HGC_SAS_TXFAIL_RETRY_CTRL),

	HISI_SAS_DEBUGFS_REG(HGC_GET_ITV_TIME),