Commit 8790ccf8 authored Jan 14, 2021 by Nathan Chancellor Committed by Thomas Bogendoerfer Jan 15, 2021

MIPS: Compare __SYNC_loongson3_war against 0



When building with clang when CONFIG_CPU_LOONGSON3_WORKAROUNDS is
enabled:

 In file included from lib/errseq.c:4:
 In file included from ./include/linux/atomic.h:7:
 ./arch/mips/include/asm/atomic.h:52:1: warning: converting the result of
 '<<' to a boolean always evaluates to true
 [-Wtautological-constant-compare]
 ATOMIC_OPS(atomic64, s64)
 ^
 ./arch/mips/include/asm/atomic.h:40:9: note: expanded from macro
 'ATOMIC_OPS'
         return cmpxchg(&v->counter, o, n);
                ^
 ./arch/mips/include/asm/cmpxchg.h:194:7: note: expanded from macro
 'cmpxchg'
         if (!__SYNC_loongson3_war)
              ^
 ./arch/mips/include/asm/sync.h:147:34: note: expanded from macro
 '__SYNC_loongson3_war'
 # define __SYNC_loongson3_war   (1 << 31)
                                    ^

While it is not wrong that the result of this shift is always true in a
boolean context, it is not a problem here. Regardless, the warning is
really noisy so rather than making the shift a boolean implicitly, use
it in an equality comparison so the shift is used as an integer value.

Fixes: 4d1dbfe6 ("MIPS: atomic: Emit Loongson3 sync workarounds within asm")
Fixes: a91f2a1d ("MIPS: cmpxchg: Omit redundant barriers for Loongson3")
Reported-by: kernel test robot <lkp@intel.com>
Signed-off-by: Nathan Chancellor <natechancellor@gmail.com>
Acked-by: Nick Desaulniers <ndesaulniers@google.com>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>

parent cabcff9b

arch/mips/include/asm/atomic.h

+1 −1

Original line number	Diff line number	Diff line
		@@ -248,7 +248,7 @@ static __inline__ int pfx##_sub_if_positive(type i, pfx##_t * v) \
		* bltz that can branch to code outside of the LL/SC loop. As \
		* such, we don't need to emit another barrier here. \
		*/ \
		if (!__SYNC_loongson3_war) \
		if (__SYNC_loongson3_war == 0) \
		smp_mb__after_atomic(); \
		\
		return result; \

arch/mips/include/asm/cmpxchg.h

+3 −3

Original line number	Diff line number	Diff line
		@@ -99,7 +99,7 @@ unsigned long __xchg(volatile void *ptr, unsigned long x, int size)
		* contains a completion barrier prior to the LL, so we don't \
		* need to emit an extra one here. \
		*/ \
		if (!__SYNC_loongson3_war) \
		if (__SYNC_loongson3_war == 0) \
		smp_mb__before_llsc(); \
		\
		__res = (__typeof__(*(ptr))) \
		@@ -191,7 +191,7 @@ unsigned long __cmpxchg(volatile void *ptr, unsigned long old,
		* contains a completion barrier prior to the LL, so we don't \
		* need to emit an extra one here. \
		*/ \
		if (!__SYNC_loongson3_war) \
		if (__SYNC_loongson3_war == 0) \
		smp_mb__before_llsc(); \
		\
		__res = cmpxchg_local((ptr), (old), (new)); \
		@@ -201,7 +201,7 @@ unsigned long __cmpxchg(volatile void *ptr, unsigned long old,
		* contains a completion barrier after the SC, so we don't \
		* need to emit an extra one here. \
		*/ \
		if (!__SYNC_loongson3_war) \
		if (__SYNC_loongson3_war == 0) \
		smp_llsc_mb(); \
		\
		__res; \