Commit 8893df29 authored by James Morse's avatar James Morse Committed by Will Deacon
Browse files

arm64/sysreg: Convert ID_MMFR0_EL1 to automatic generation 



Convert ID_MMFR0_EL1 to be automatically generated as per DDI0487I.a,
no functional changes.

Reviewed-by: default avatarMark Brown <broonie@kernel.org>
Signed-off-by: default avatarJames Morse <james.morse@arm.com>
Link: https://lore.kernel.org/r/20221130171637.718182-18-james.morse@arm.com


Signed-off-by: default avatarWill Deacon <will@kernel.org>
parent 7587cdef

arch/arm64/include/asm/sysreg.h

+0 −10
Original line number Diff line number Diff line
@@ -171,7 +171,6 @@ 
#define SYS_ID_DFR0_EL1			sys_reg(3, 0, 0, 1, 2)

#define SYS_ID_DFR1_EL1			sys_reg(3, 0, 0, 3, 5)

#define SYS_ID_AFR0_EL1			sys_reg(3, 0, 0, 1, 3)

#define SYS_ID_MMFR0_EL1		sys_reg(3, 0, 0, 1, 4)

#define SYS_ID_MMFR1_EL1		sys_reg(3, 0, 0, 1, 5)

#define SYS_ID_MMFR2_EL1		sys_reg(3, 0, 0, 1, 6)

#define SYS_ID_MMFR3_EL1		sys_reg(3, 0, 0, 1, 7)
@@ -731,15 +730,6 @@ 
#define ID_ISAR6_EL1_DP_SHIFT		4

#define ID_ISAR6_EL1_JSCVT_SHIFT	0



#define ID_MMFR0_EL1_InnerShr_SHIFT	28

#define ID_MMFR0_EL1_FCSE_SHIFT		24

#define ID_MMFR0_EL1_AuxReg_SHIFT	20

#define ID_MMFR0_EL1_TCM_SHIFT		16

#define ID_MMFR0_EL1_ShareLvl_SHIFT	12

#define ID_MMFR0_EL1_OuterShr_SHIFT	8

#define ID_MMFR0_EL1_PMSA_SHIFT		4

#define ID_MMFR0_EL1_VMSA_SHIFT		0



#define ID_MMFR4_EL1_EVT_SHIFT		28

#define ID_MMFR4_EL1_CCIDX_SHIFT	24

#define ID_MMFR4_EL1_LSM_SHIFT		20

arch/arm64/tools/sysreg

+47 −0
Original line number Diff line number Diff line
@@ -46,6 +46,53 @@ 
# feature that introduces them (eg, FEAT_LS64_ACCDATA introduces enumeration

# item ACCDATA) though it may be more taseful to do something else.



Sysreg ID_MMFR0_EL1	3	0	0	1	4

Res0	63:32

Enum	31:28	InnerShr

	0b0000	NC

	0b0001	HW

	0b1111	IGNORED

EndEnum

Enum	27:24	FCSE

	0b0000	NI

	0b0001	IMP

EndEnum

Enum	23:20	AuxReg

	0b0000	NI

	0b0001	ACTLR

	0b0010	AIFSR

EndEnum

Enum	19:16	TCM

	0b0000	NI

	0b0001	IMPDEF

	0b0010	TCM

	0b0011	TCM_DMA

EndEnum

Enum	15:12	ShareLvl

	0b0000	ONE

	0b0001	TWO

EndEnum

Enum	11:8	OuterShr

	0b0000	NC

	0b0001	HW

	0b1111	IGNORED

EndEnum

Enum	7:4	PMSA

	0b0000	NI

	0b0001	IMPDEF

	0b0010	PMSAv6

	0b0011	PMSAv7

EndEnum

Enum	3:0	VMSA

	0b0000	NI

	0b0001	IMPDEF

	0b0010	VMSAv6

	0b0011	VMSAv7

	0b0100	VMSAv7_PXN

	0b0101	VMSAv7_LONG

EndEnum

EndSysreg



Sysreg	ID_AA64PFR0_EL1	3	0	0	4	0

Enum	63:60	CSV3

	0b0000	NI