Commit 88d7c71e authored by Pierre-Louis Bossart's avatar Pierre-Louis Bossart Committed by Vinod Koul
Browse files

soundwire: bus: update multi-link definition with hw sync details 



Hardware-based synchronization is typically required when the
bus->multi_link flag is set.

On Intel platforms, when the Cadence IP is configured in 'Multi Master
Mode', the hardware synchronization is required even when a stream
only uses a single segment. The existing code only deal with hardware
synchronization when a stream uses more than one segment so to remain
backwards compatible we add a configuration threshold. For Intel cases
this threshold will be set to one, other platforms may be able to use
the SSP-based sync in those cases.

Signed-off-by: default avatarPierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Signed-off-by: default avatarBard Liao <yung-chuan.liao@linux.intel.com>
Link: https://lore.kernel.org/r/20200901150556.19432-6-yung-chuan.liao@linux.intel.com


Signed-off-by: default avatarVinod Koul <vkoul@kernel.org>
parent d78071b4

include/linux/soundwire/sdw.h

+6 −0
Original line number Diff line number Diff line
@@ -828,6 +828,11 @@ struct sdw_master_ops { 
 * @multi_link: Store bus property that indicates if multi links

 * are supported. This flag is populated by drivers after reading

 * appropriate firmware (ACPI/DT).

 * @hw_sync_min_links: Number of links used by a stream above which

 * hardware-based synchronization is required. This value is only

 * meaningful if multi_link is set. If set to 1, hardware-based

 * synchronization will be used even if a stream only uses a single

 * SoundWire segment.

 */

struct sdw_bus {

	struct device *dev;
@@ -851,6 +856,7 @@ struct sdw_bus { 
	unsigned int clk_stop_timeout;

	u32 bank_switch_timeout;

	bool multi_link;

	int hw_sync_min_links;

};



int sdw_bus_master_add(struct sdw_bus *bus, struct device *parent,