Commit 88e7b76e authored by Divy Le Ray's avatar Divy Le Ray Committed by David S. Miller
Browse files

cxgb3: fix Gen2 pci default settings 



Modify control register settings to accommodate the bridge's max read
requset size.

Signed-off-by: default avatarDivy Le Ray <divy@chelsio.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 9450526a

drivers/net/cxgb3/t3_hw.c

+12 −1
Original line number Diff line number Diff line
@@ -3465,7 +3465,7 @@ static void config_pcie(struct adapter *adap) 
		{201, 321, 258, 450, 834, 1602}

	};



	u16 val;

	u16 val, devid;

	unsigned int log2_width, pldsize;

	unsigned int fst_trn_rx, fst_trn_tx, acklat, rpllmt;
@@ -3473,6 +3473,17 @@ static void config_pcie(struct adapter *adap) 
			     adap->params.pci.pcie_cap_addr + PCI_EXP_DEVCTL,

			     &val);

	pldsize = (val & PCI_EXP_DEVCTL_PAYLOAD) >> 5;



	pci_read_config_word(adap->pdev, 0x2, &devid);

	if (devid == 0x37) {

		pci_write_config_word(adap->pdev,

				      adap->params.pci.pcie_cap_addr +

				      PCI_EXP_DEVCTL,

				      val & ~PCI_EXP_DEVCTL_READRQ &

				      ~PCI_EXP_DEVCTL_PAYLOAD);

		pldsize = 0;

	}



	pci_read_config_word(adap->pdev,

			     adap->params.pci.pcie_cap_addr + PCI_EXP_LNKCTL,

			     &val);