Commit 8b6a006c authored by Lad Prabhakar's avatar Lad Prabhakar Committed by Geert Uytterhoeven
Browse files

arm64: dts: renesas: Drop specifying the GIC_CPU_MASK_SIMPLE() for GICv3 systems 



The GICv3 interrupts binding does not have a cpumask. The CPU mask only
applies to pre-GICv3. So just drop using them from GICv3 systems.

Signed-off-by: default avatarLad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20230206002136.29401-1-prabhakar.mahadev-lad.rj@bp.renesas.com


Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
parent c2b92d7e

arch/arm64/boot/dts/renesas/r8a779a0.dtsi

+5 −6
Original line number Diff line number Diff line
@@ -2209,8 +2209,7 @@ gic: interrupt-controller@f1000000 { 
			interrupt-controller;

			reg = <0x0 0xf1000000 0 0x20000>,

			      <0x0 0xf1060000 0 0x110000>;

			interrupts = <GIC_PPI 9

				      (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;

			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;

		};



		fcpvd0: fcp@fea10000 {
@@ -2857,9 +2856,9 @@ sensor5_crit: sensor5-crit { 


	timer {

		compatible = "arm,armv8-timer";

		interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,

				      <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,

				      <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,

				      <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;

		interrupts-extended = <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,

				      <&gic GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,

				      <&gic GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,

				      <&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;

	};

};

arch/arm64/boot/dts/renesas/r8a779f0.dtsi

+5 −6
Original line number Diff line number Diff line
@@ -1108,8 +1108,7 @@ gic: interrupt-controller@f1000000 { 
			interrupt-controller;

			reg = <0x0 0xf1000000 0 0x20000>,

			      <0x0 0xf1060000 0 0x110000>;

			interrupts = <GIC_PPI 9

				      (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;

			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;

		};



		prr: chipid@fff00044 {
@@ -1164,10 +1163,10 @@ sensor3_crit: sensor3-crit { 


	timer {

		compatible = "arm,armv8-timer";

		interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,

				      <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,

				      <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,

				      <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;

		interrupts-extended = <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,

				      <&gic GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,

				      <&gic GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,

				      <&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;

	};



	ufs30_clk: ufs30-clk {

arch/arm64/boot/dts/renesas/r8a779g0.dtsi

+5 −6
Original line number Diff line number Diff line
@@ -1262,8 +1262,7 @@ gic: interrupt-controller@f1000000 { 
			interrupt-controller;

			reg = <0x0 0xf1000000 0 0x20000>,

			      <0x0 0xf1060000 0 0x110000>;

			interrupts = <GIC_PPI 9

				      (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;

			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;

		};



		fcpvd0: fcp@fea10000 {
@@ -1404,9 +1403,9 @@ prr: chipid@fff00044 { 


	timer {

		compatible = "arm,armv8-timer";

		interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,

				      <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,

				      <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,

				      <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;

		interrupts-extended = <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,

				      <&gic GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,

				      <&gic GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,

				      <&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;

	};

};

arch/arm64/boot/dts/renesas/r9a07g043u.dtsi

+4 −4
Original line number Diff line number Diff line
@@ -47,10 +47,10 @@ psci { 


	timer {

		compatible = "arm,armv8-timer";

		interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,

				      <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,

				      <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,

				      <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;

		interrupts-extended = <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,

				      <&gic GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,

				      <&gic GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,

				      <&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;

	};

};

arch/arm64/boot/dts/renesas/r9a07g044.dtsi

+4 −4
Original line number Diff line number Diff line
@@ -1066,9 +1066,9 @@ target: trip-point { 


	timer {

		compatible = "arm,armv8-timer";

		interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,

				      <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,

				      <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,

				      <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;

		interrupts-extended = <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,

				      <&gic GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,

				      <&gic GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,

				      <&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;

	};

};