Commit 8bf6e202 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'drm-intel-next-2023-03-07' of git://anongit.freedesktop.org/drm/drm-intel into drm-next 



Cross-subsystem Changes:
- MEI patches to fix suspend/resume issues with the i915's PXP. (Alexander)

Driver Changes:
- Registers helpers and clean-ups. (Lucas)
- PXP fixes and clean-ups. (Alan, Alexander)
- CDCLK related fixes and w/a (Chaitanya, Stanislav)
- Move display code to use RMW whenever possible (Andrzej)
- PSR fixes (Jouni, Ville)
- Implement async_flip mode per plane tracking (Andrzej)
- Remove pre-production Workarounds (Matt)
- HDMI related fixes (Ankit)
- LVDS cleanup (Ville)
- Watermark fixes and cleanups (Ville, Jani, Stanilav)
- DMC code related fixes, cleanups and improvements (Jani)
- Implement fb_dirty for PSR,FBC,DRRS fixes (Jouni)
- Initial DSB improvements targeting LUTs loading (Ville)
- HWMON related fixes (Ashutosh)
- PCI ID updates (Jonathan, Matt Roper)
- Fix leak in scatterlist (Matt Atwood)
- Fix eDP+DSI dual panel systems (Ville)
- Cast iomem to avoid sparese warnings (Jani)
- Set default backlight controller index (Jani)
- More MTL enabling (RK)
- Conversion of display dev_priv towards i915 (Nirmoy)
- Improvements in log/debug messages (Ville)
- Increase slice_height for DP VDSC (Suraj)
- VBT ports improvements (Ville)
- Fix platforms without Display (Imre)
- Other generic display code clean-ups (Ville, Jani, Rodrigo)
- Add RPL-U sub platform (Chaitanya)
- Add inverted backlight quirk for HP 14-r206nv (Mavroudis)
- Transcoder timing improvements (Ville)
- Track audio state per-transcoder (Ville)
- Error/underrun interrupt fixes (Ville)
- Update combo PHY init sequence (Matt Roper)
- Get HDR DPCD refresh timeout (Ville)
- Vblank improvements (Ville)
- DSS fixes and cleanups (Jani)
- PM code cleanup (Jani)
- Split display parts related to RPS (Jani)

Signed-off-by: default avatarDave Airlie <airlied@redhat.com>

From: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/ZAez4aekcob8fTeh@intel.com
parents faf0d83e 4b736ed4

drivers/gpu/drm/i915/Makefile

+3 −0
Original line number Diff line number Diff line
@@ -239,6 +239,7 @@ i915-y += \ 
	display/intel_display_power.o \

	display/intel_display_power_map.o \

	display/intel_display_power_well.o \

	display/intel_display_rps.o \

	display/intel_dmc.o \

	display/intel_dpio_phy.o \

	display/intel_dpll.o \
@@ -269,7 +270,9 @@ i915-y += \ 
	display/intel_tc.o \

	display/intel_vblank.o \

	display/intel_vga.o \

	display/intel_wm.o \

	display/i9xx_plane.o \

	display/i9xx_wm.o \

	display/skl_scaler.o \

	display/skl_universal_plane.o \

	display/skl_watermark.o

drivers/gpu/drm/i915/display/g4x_dp.c

+17 −36
Original line number Diff line number Diff line
@@ -17,6 +17,7 @@ 
#include "intel_display_power.h"

#include "intel_display_types.h"

#include "intel_dp.h"

#include "intel_dp_aux.h"

#include "intel_dp_link_training.h"

#include "intel_dpio_phy.h"

#include "intel_fifo_underrun.h"
@@ -136,16 +137,12 @@ static void intel_dp_prepare(struct intel_encoder *encoder, 


		intel_dp->DP |= DP_PIPE_SEL_IVB(crtc->pipe);

	} else if (HAS_PCH_CPT(dev_priv) && port != PORT_A) {

		u32 trans_dp;



		intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;



		trans_dp = intel_de_read(dev_priv, TRANS_DP_CTL(crtc->pipe));

		if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))

			trans_dp |= TRANS_DP_ENH_FRAMING;

		else

			trans_dp &= ~TRANS_DP_ENH_FRAMING;

		intel_de_write(dev_priv, TRANS_DP_CTL(crtc->pipe), trans_dp);

		intel_de_rmw(dev_priv, TRANS_DP_CTL(crtc->pipe),

			     TRANS_DP_ENH_FRAMING,

			     drm_dp_enhanced_frame_cap(intel_dp->dpcd) ?

			     TRANS_DP_ENH_FRAMING : 0);

	} else {

		if (IS_G4X(dev_priv) && pipe_config->limited_color_range)

			intel_dp->DP |= DP_COLOR_RANGE_16_235;
@@ -1200,29 +1197,6 @@ static bool g4x_digital_port_connected(struct intel_encoder *encoder) 
	return intel_de_read(dev_priv, PORT_HOTPLUG_STAT) & bit;

}



static bool gm45_digital_port_connected(struct intel_encoder *encoder)

{

	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);

	u32 bit;



	switch (encoder->hpd_pin) {

	case HPD_PORT_B:

		bit = PORTB_HOTPLUG_LIVE_STATUS_GM45;

		break;

	case HPD_PORT_C:

		bit = PORTC_HOTPLUG_LIVE_STATUS_GM45;

		break;

	case HPD_PORT_D:

		bit = PORTD_HOTPLUG_LIVE_STATUS_GM45;

		break;

	default:

		MISSING_CASE(encoder->hpd_pin);

		return false;

	}



	return intel_de_read(dev_priv, PORT_HOTPLUG_STAT) & bit;

}



static bool ilk_digital_port_connected(struct intel_encoder *encoder)

{

	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
@@ -1279,11 +1253,19 @@ static const struct drm_encoder_funcs intel_dp_enc_funcs = { 
bool g4x_dp_init(struct drm_i915_private *dev_priv,

		 i915_reg_t output_reg, enum port port)

{

	const struct intel_bios_encoder_data *devdata;

	struct intel_digital_port *dig_port;

	struct intel_encoder *intel_encoder;

	struct drm_encoder *encoder;

	struct intel_connector *intel_connector;



	devdata = intel_bios_encoder_data_lookup(dev_priv, port);



	/* FIXME bail? */

	if (!devdata)

		drm_dbg_kms(&dev_priv->drm, "No VBT child device for DP-%c\n",

			    port_name(port));



	dig_port = kzalloc(sizeof(*dig_port), GFP_KERNEL);

	if (!dig_port)

		return false;
@@ -1295,6 +1277,8 @@ bool g4x_dp_init(struct drm_i915_private *dev_priv, 
	intel_encoder = &dig_port->base;

	encoder = &intel_encoder->base;



	intel_encoder->devdata = devdata;



	mutex_init(&dig_port->hdcp_mutex);



	if (drm_encoder_init(&dev_priv->drm, &intel_encoder->base,
@@ -1377,9 +1361,6 @@ bool g4x_dp_init(struct drm_i915_private *dev_priv, 
	dig_port->hpd_pulse = intel_dp_hpd_pulse;



	if (HAS_GMCH(dev_priv)) {

		if (IS_GM45(dev_priv))

			dig_port->connected = gm45_digital_port_connected;

		else

		dig_port->connected = g4x_digital_port_connected;

	} else {

		if (port == PORT_A)
@@ -1391,7 +1372,7 @@ bool g4x_dp_init(struct drm_i915_private *dev_priv, 
	if (port != PORT_A)

		intel_infoframe_init(dig_port);



	dig_port->aux_ch = intel_bios_port_aux_ch(dev_priv, port);

	dig_port->aux_ch = intel_dp_aux_ch(intel_encoder);

	if (!intel_dp_init_connector(dig_port, intel_connector))

		goto err_init_connector;

drivers/gpu/drm/i915/display/g4x_hdmi.c

+16 −5
Original line number Diff line number Diff line
@@ -13,6 +13,7 @@ 
#include "intel_de.h"

#include "intel_display_power.h"

#include "intel_display_types.h"

#include "intel_dp_aux.h"

#include "intel_dpio_phy.h"

#include "intel_fifo_underrun.h"

#include "intel_hdmi.h"
@@ -273,8 +274,8 @@ static void cpt_enable_hdmi(struct intel_atomic_state *state, 
	 */



	if (pipe_config->pipe_bpp > 24) {

		intel_de_write(dev_priv, TRANS_CHICKEN1(pipe),

			       intel_de_read(dev_priv, TRANS_CHICKEN1(pipe)) | TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE);

		intel_de_rmw(dev_priv, TRANS_CHICKEN1(pipe),

			     0, TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE);



		temp &= ~SDVO_COLOR_FORMAT_MASK;

		temp |= SDVO_COLOR_FORMAT_8bpc;
@@ -290,8 +291,8 @@ static void cpt_enable_hdmi(struct intel_atomic_state *state, 
		intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp);

		intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg);



		intel_de_write(dev_priv, TRANS_CHICKEN1(pipe),

			       intel_de_read(dev_priv, TRANS_CHICKEN1(pipe)) & ~TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE);

		intel_de_rmw(dev_priv, TRANS_CHICKEN1(pipe),

			     TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE, 0);

	}



	drm_WARN_ON(&dev_priv->drm, pipe_config->has_audio &&
@@ -548,10 +549,18 @@ intel_hdmi_hotplug(struct intel_encoder *encoder, 
void g4x_hdmi_init(struct drm_i915_private *dev_priv,

		   i915_reg_t hdmi_reg, enum port port)

{

	const struct intel_bios_encoder_data *devdata;

	struct intel_digital_port *dig_port;

	struct intel_encoder *intel_encoder;

	struct intel_connector *intel_connector;



	devdata = intel_bios_encoder_data_lookup(dev_priv, port);



	/* FIXME bail? */

	if (!devdata)

		drm_dbg_kms(&dev_priv->drm, "No VBT child device for HDMI-%c\n",

			    port_name(port));



	dig_port = kzalloc(sizeof(*dig_port), GFP_KERNEL);

	if (!dig_port)

		return;
@@ -564,6 +573,8 @@ void g4x_hdmi_init(struct drm_i915_private *dev_priv, 


	intel_encoder = &dig_port->base;



	intel_encoder->devdata = devdata;



	mutex_init(&dig_port->hdcp_mutex);



	drm_encoder_init(&dev_priv->drm, &intel_encoder->base,
@@ -629,6 +640,6 @@ void g4x_hdmi_init(struct drm_i915_private *dev_priv, 


	intel_infoframe_init(dig_port);



	dig_port->aux_ch = intel_bios_port_aux_ch(dev_priv, port);

	dig_port->aux_ch = intel_dp_aux_ch(intel_encoder);

	intel_hdmi_init_connector(dig_port, intel_connector);

}

drivers/gpu/drm/i915/display/i9xx_wm.c

0 → 100644
+4047 −0

File added.

Preview size limit exceeded, changes collapsed.

drivers/gpu/drm/i915/display/i9xx_wm.h

0 → 100644
+21 −0
Original line number Diff line number Diff line 
/* SPDX-License-Identifier: MIT */

/*

 * Copyright © 2023 Intel Corporation

 */



#ifndef __I9XX_WM_H__

#define __I9XX_WM_H__



#include <linux/types.h>



struct drm_i915_private;

struct intel_crtc_state;

struct intel_plane_state;



int ilk_wm_max_level(const struct drm_i915_private *i915);

bool ilk_disable_lp_wm(struct drm_i915_private *i915);

void ilk_wm_sanitize(struct drm_i915_private *i915);

bool intel_set_memory_cxsr(struct drm_i915_private *i915, bool enable);

void i9xx_wm_init(struct drm_i915_private *i915);



#endif /* __I9XX_WM_H__ */