Merge branch 'for-5.20/dt-bindings' into for-5.20/memory (8c2261e9) · Commits · jan.koester / Linux

Documentation/devicetree/bindings/arm/tegra/nvidia,tegra194-axi2apb.yaml

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		# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
		%YAML 1.2
		---
		$id: "http://devicetree.org/schemas/arm/tegra/nvidia,tegra194-axi2apb.yaml#"
		$schema: "http://devicetree.org/meta-schemas/core.yaml#"

		title: NVIDIA Tegra194 AXI2APB bridge

		maintainers:
		- Sumit Gupta <sumitg@nvidia.com>

		properties:
		$nodename:
		pattern: "^axi2apb@([0-9a-f]+)$"

		compatible:
		enum:
		- nvidia,tegra194-axi2apb

		reg:
		maxItems: 6
		description: Physical base address and length of registers for all bridges

		additionalProperties: false

		required:
		- compatible
		- reg

		examples:
		- \|
		axi2apb: axi2apb@2390000 {
		compatible = "nvidia,tegra194-axi2apb";
		reg = <0x02390000 0x1000>,
		<0x023a0000 0x1000>,
		<0x023b0000 0x1000>,
		<0x023c0000 0x1000>,
		<0x023d0000 0x1000>,
		<0x023e0000 0x1000>;
		};

Documentation/devicetree/bindings/arm/tegra/nvidia,tegra194-cbb.yaml

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		# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
		%YAML 1.2
		---
		$id: "http://devicetree.org/schemas/arm/tegra/nvidia,tegra194-cbb.yaml#"
		$schema: "http://devicetree.org/meta-schemas/core.yaml#"

		title: NVIDIA Tegra194 CBB 1.0 bindings

		maintainers:
		- Sumit Gupta <sumitg@nvidia.com>

		description: \|+
		The Control Backbone (CBB) is comprised of the physical path from an
		initiator to a target's register configuration space. CBB 1.0 has
		multiple hierarchical sub-NOCs (Network-on-Chip) and connects various
		initiators and targets using different bridges like AXIP2P, AXI2APB.

		This driver handles errors due to illegal register accesses reported
		by the NOCs inside the CBB. NOCs reporting errors are cluster NOCs
		"AON-NOC, SCE-NOC, RCE-NOC, BPMP-NOC, CV-NOC" and "CBB Central NOC"
		which is the main NOC.

		By default, the access issuing initiator is informed about the error
		using SError or Data Abort exception unless the ERD (Error Response
		Disable) is enabled/set for that initiator. If the ERD is enabled, then
		SError or Data Abort is masked and the error is reported with interrupt.

		- For CCPLEX (CPU Complex) initiator, the driver sets ERD bit. So, the
		errors due to illegal accesses from CCPLEX are reported by interrupts.
		If ERD is not set, then error is reported by SError.
		- For other initiators, the ERD is disabled. So, the access issuing
		initiator is informed about the illegal access by Data Abort exception.
		In addition, an interrupt is also generated to CCPLEX. These initiators
		include all engines using Cortex-R5 (which is ARMv7 CPU cluster) and
		engines like TSEC (Security co-processor), NVDEC (NVIDIA Video Decoder
		engine) etc which can initiate transactions.

		The driver prints relevant debug information like Error Code, Error
		Description, Master, Address, AXI ID, Cache, Protection, Security Group
		etc on receiving error notification.

		properties:
		$nodename:
		pattern: "^[a-z]+-noc@[0-9a-f]+$"

		compatible:
		enum:
		- nvidia,tegra194-cbb-noc
		- nvidia,tegra194-aon-noc
		- nvidia,tegra194-bpmp-noc
		- nvidia,tegra194-rce-noc
		- nvidia,tegra194-sce-noc

		reg:
		maxItems: 1

		interrupts:
		description:
		CCPLEX receives secure or nonsecure interrupt depending on error type.
		A secure interrupt is received for SEC(firewall) & SLV errors and a
		non-secure interrupt is received for TMO & DEC errors.
		items:
		- description: non-secure interrupt
		- description: secure interrupt

		nvidia,axi2apb:
		$ref: '/schemas/types.yaml#/definitions/phandle'
		description:
		Specifies the node having all axi2apb bridges which need to be checked
		for any error logged in their status register.

		nvidia,apbmisc:
		$ref: '/schemas/types.yaml#/definitions/phandle'
		description:
		Specifies the apbmisc node which need to be used for reading the ERD
		register.

		additionalProperties: false

		required:
		- compatible
		- reg
		- interrupts
		- nvidia,apbmisc

		examples:
		- \|
		#include <dt-bindings/interrupt-controller/arm-gic.h>

		cbb-noc@2300000 {
		compatible = "nvidia,tegra194-cbb-noc";
		reg = <0x02300000 0x1000>;
		interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>,
		<GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>;
		nvidia,axi2apb = <&axi2apb>;
		nvidia,apbmisc = <&apbmisc>;
		};

Documentation/devicetree/bindings/arm/tegra/nvidia,tegra234-cbb.yaml

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		# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
		%YAML 1.2
		---
		$id: "http://devicetree.org/schemas/arm/tegra/nvidia,tegra234-cbb.yaml#"
		$schema: "http://devicetree.org/meta-schemas/core.yaml#"

		title: NVIDIA Tegra CBB 2.0 bindings

		maintainers:
		- Sumit Gupta <sumitg@nvidia.com>

		description: \|+
		The Control Backbone (CBB) is comprised of the physical path from an
		initiator to a target's register configuration space. CBB 2.0 consists
		of multiple sub-blocks connected to each other to create a topology.
		The Tegra234 SoC has different fabrics based on CBB 2.0 architecture
		which include cluster fabrics BPMP, AON, PSC, SCE, RCE, DCE, FSI and
		"CBB central fabric".

		In CBB 2.0, each initiator which can issue transactions connects to a
		Root Master Node (MN) before it connects to any other element of the
		fabric. Each Root MN contains a Error Monitor (EM) which detects and
		logs error. Interrupts from various EM blocks are collated by Error
		Notifier (EN) which is per fabric and presents a single interrupt from
		fabric to the SoC interrupt controller.

		The driver handles errors from CBB due to illegal register accesses
		and prints debug information about failed transaction on receiving
		the interrupt from EN. Debug information includes Error Code, Error
		Description, MasterID, Fabric, SlaveID, Address, Cache, Protection,
		Security Group etc on receiving error notification.

		If the Error Response Disable (ERD) is set/enabled for an initiator,
		then SError or Data abort exception error response is masked and an
		interrupt is used for reporting errors due to illegal accesses from
		that initiator. The value returned on read failures is '0xFFFFFFFF'
		for compatibility with PCIE.

		properties:
		$nodename:
		pattern: "^[a-z]+-fabric@[0-9a-f]+$"

		compatible:
		enum:
		- nvidia,tegra234-aon-fabric
		- nvidia,tegra234-bpmp-fabric
		- nvidia,tegra234-cbb-fabric
		- nvidia,tegra234-dce-fabric
		- nvidia,tegra234-rce-fabric
		- nvidia,tegra234-sce-fabric

		reg:
		maxItems: 1

		interrupts:
		items:
		- description: secure interrupt from error notifier

		additionalProperties: false

		required:
		- compatible
		- reg
		- interrupts

		examples:
		- \|
		#include <dt-bindings/interrupt-controller/arm-gic.h>

		cbb-fabric@1300000 {
		compatible = "nvidia,tegra234-cbb-fabric";
		reg = <0x13a00000 0x400000>;
		interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>;
		};

include/dt-bindings/clock/tegra234-clock.h

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Original line number	Diff line number	Diff line
		@@ -164,10 +164,111 @@
		#define TEGRA234_CLK_PEX1_C5_CORE 225U
		/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLC4_BASE */
		#define TEGRA234_CLK_PLLC4 237U
		/** @brief RX clock recovered from MGBE0 lane input */
		#define TEGRA234_CLK_MGBE0_RX_INPUT 248U
		/** @brief RX clock recovered from MGBE1 lane input */
		#define TEGRA234_CLK_MGBE1_RX_INPUT 249U
		/** @brief RX clock recovered from MGBE2 lane input */
		#define TEGRA234_CLK_MGBE2_RX_INPUT 250U
		/** @brief RX clock recovered from MGBE3 lane input */
		#define TEGRA234_CLK_MGBE3_RX_INPUT 251U
		/** @brief 32K input clock provided by PMIC */
		#define TEGRA234_CLK_CLK_32K 289U
		/** @brief Monitored branch of MBGE0 RX input clock */
		#define TEGRA234_CLK_MGBE0_RX_INPUT_M 357U
		/** @brief Monitored branch of MBGE1 RX input clock */
		#define TEGRA234_CLK_MGBE1_RX_INPUT_M 358U
		/** @brief Monitored branch of MBGE2 RX input clock */
		#define TEGRA234_CLK_MGBE2_RX_INPUT_M 359U
		/** @brief Monitored branch of MBGE3 RX input clock */
		#define TEGRA234_CLK_MGBE3_RX_INPUT_M 360U
		/** @brief Monitored branch of MGBE0 RX PCS mux output */
		#define TEGRA234_CLK_MGBE0_RX_PCS_M 361U
		/** @brief Monitored branch of MGBE1 RX PCS mux output */
		#define TEGRA234_CLK_MGBE1_RX_PCS_M 362U
		/** @brief Monitored branch of MGBE2 RX PCS mux output */
		#define TEGRA234_CLK_MGBE2_RX_PCS_M 363U
		/** @brief Monitored branch of MGBE3 RX PCS mux output */
		#define TEGRA234_CLK_MGBE3_RX_PCS_M 364U
		/** @brief RX PCS clock recovered from MGBE0 lane input */
		#define TEGRA234_CLK_MGBE0_RX_PCS_INPUT 369U
		/** @brief RX PCS clock recovered from MGBE1 lane input */
		#define TEGRA234_CLK_MGBE1_RX_PCS_INPUT 370U
		/** @brief RX PCS clock recovered from MGBE2 lane input */
		#define TEGRA234_CLK_MGBE2_RX_PCS_INPUT 371U
		/** @brief RX PCS clock recovered from MGBE3 lane input */
		#define TEGRA234_CLK_MGBE3_RX_PCS_INPUT 372U
		/** @brief output of mux controlled by GBE_UPHY_MGBE0_RX_PCS_CLK_SRC_SEL */
		#define TEGRA234_CLK_MGBE0_RX_PCS 373U
		/** @brief GBE_UPHY_MGBE0_TX_CLK divider gated output */
		#define TEGRA234_CLK_MGBE0_TX 374U
		/** @brief GBE_UPHY_MGBE0_TX_PCS_CLK divider gated output */
		#define TEGRA234_CLK_MGBE0_TX_PCS 375U
		/** @brief GBE_UPHY_MGBE0_MAC_CLK divider output */
		#define TEGRA234_CLK_MGBE0_MAC_DIVIDER 376U
		/** @brief GBE_UPHY_MGBE0_MAC_CLK gate output */
		#define TEGRA234_CLK_MGBE0_MAC 377U
		/** @brief GBE_UPHY_MGBE0_MACSEC_CLK gate output */
		#define TEGRA234_CLK_MGBE0_MACSEC 378U
		/** @brief GBE_UPHY_MGBE0_EEE_PCS_CLK gate output */
		#define TEGRA234_CLK_MGBE0_EEE_PCS 379U
		/** @brief GBE_UPHY_MGBE0_APP_CLK gate output */
		#define TEGRA234_CLK_MGBE0_APP 380U
		/** @brief GBE_UPHY_MGBE0_PTP_REF_CLK divider gated output */
		#define TEGRA234_CLK_MGBE0_PTP_REF 381U
		/** @brief output of mux controlled by GBE_UPHY_MGBE1_RX_PCS_CLK_SRC_SEL */
		#define TEGRA234_CLK_MGBE1_RX_PCS 382U
		/** @brief GBE_UPHY_MGBE1_TX_CLK divider gated output */
		#define TEGRA234_CLK_MGBE1_TX 383U
		/** @brief GBE_UPHY_MGBE1_TX_PCS_CLK divider gated output */
		#define TEGRA234_CLK_MGBE1_TX_PCS 384U
		/** @brief GBE_UPHY_MGBE1_MAC_CLK divider output */
		#define TEGRA234_CLK_MGBE1_MAC_DIVIDER 385U
		/** @brief GBE_UPHY_MGBE1_MAC_CLK gate output */
		#define TEGRA234_CLK_MGBE1_MAC 386U
		/** @brief GBE_UPHY_MGBE1_EEE_PCS_CLK gate output */
		#define TEGRA234_CLK_MGBE1_EEE_PCS 388U
		/** @brief GBE_UPHY_MGBE1_APP_CLK gate output */
		#define TEGRA234_CLK_MGBE1_APP 389U
		/** @brief GBE_UPHY_MGBE1_PTP_REF_CLK divider gated output */
		#define TEGRA234_CLK_MGBE1_PTP_REF 390U
		/** @brief output of mux controlled by GBE_UPHY_MGBE2_RX_PCS_CLK_SRC_SEL */
		#define TEGRA234_CLK_MGBE2_RX_PCS 391U
		/** @brief GBE_UPHY_MGBE2_TX_CLK divider gated output */
		#define TEGRA234_CLK_MGBE2_TX 392U
		/** @brief GBE_UPHY_MGBE2_TX_PCS_CLK divider gated output */
		#define TEGRA234_CLK_MGBE2_TX_PCS 393U
		/** @brief GBE_UPHY_MGBE2_MAC_CLK divider output */
		#define TEGRA234_CLK_MGBE2_MAC_DIVIDER 394U
		/** @brief GBE_UPHY_MGBE2_MAC_CLK gate output */
		#define TEGRA234_CLK_MGBE2_MAC 395U
		/** @brief GBE_UPHY_MGBE2_EEE_PCS_CLK gate output */
		#define TEGRA234_CLK_MGBE2_EEE_PCS 397U
		/** @brief GBE_UPHY_MGBE2_APP_CLK gate output */
		#define TEGRA234_CLK_MGBE2_APP 398U
		/** @brief GBE_UPHY_MGBE2_PTP_REF_CLK divider gated output */
		#define TEGRA234_CLK_MGBE2_PTP_REF 399U
		/** @brief output of mux controlled by GBE_UPHY_MGBE3_RX_PCS_CLK_SRC_SEL */
		#define TEGRA234_CLK_MGBE3_RX_PCS 400U
		/** @brief GBE_UPHY_MGBE3_TX_CLK divider gated output */
		#define TEGRA234_CLK_MGBE3_TX 401U
		/** @brief GBE_UPHY_MGBE3_TX_PCS_CLK divider gated output */
		#define TEGRA234_CLK_MGBE3_TX_PCS 402U
		/** @brief GBE_UPHY_MGBE3_MAC_CLK divider output */
		#define TEGRA234_CLK_MGBE3_MAC_DIVIDER 403U
		/** @brief GBE_UPHY_MGBE3_MAC_CLK gate output */
		#define TEGRA234_CLK_MGBE3_MAC 404U
		/** @brief GBE_UPHY_MGBE3_MACSEC_CLK gate output */
		#define TEGRA234_CLK_MGBE3_MACSEC 405U
		/** @brief GBE_UPHY_MGBE3_EEE_PCS_CLK gate output */
		#define TEGRA234_CLK_MGBE3_EEE_PCS 406U
		/** @brief GBE_UPHY_MGBE3_APP_CLK gate output */
		#define TEGRA234_CLK_MGBE3_APP 407U
		/** @brief GBE_UPHY_MGBE3_PTP_REF_CLK divider gated output */
		#define TEGRA234_CLK_MGBE3_PTP_REF 408U
		/** @brief CLK_RST_CONTROLLER_AZA2XBITCLK_OUT_SWITCH_DIVIDER switch divider output (aza_2xbitclk) */
		#define TEGRA234_CLK_AZA_2XBIT 457U
		/** @brief aza_2xbitclk / 2 (aza_bitclk) */
		#define TEGRA234_CLK_AZA_BIT 458U

		#endif

include/dt-bindings/memory/tegra234-mc.h

+21 −0

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		@@ -11,11 +11,16 @@
		/* NISO0 stream IDs */
		#define TEGRA234_SID_APE 0x02
		#define TEGRA234_SID_HDA 0x03
		#define TEGRA234_SID_GPCDMA 0x04
		#define TEGRA234_SID_MGBE 0x06
		#define TEGRA234_SID_PCIE0 0x12
		#define TEGRA234_SID_PCIE4 0x13
		#define TEGRA234_SID_PCIE5 0x14
		#define TEGRA234_SID_PCIE6 0x15
		#define TEGRA234_SID_PCIE9 0x1f
		#define TEGRA234_SID_MGBE_VF1 0x49
		#define TEGRA234_SID_MGBE_VF2 0x4a
		#define TEGRA234_SID_MGBE_VF3 0x4b

		/* NISO1 stream IDs */
		#define TEGRA234_SID_SDMMC4 0x02
		@@ -61,8 +66,24 @@
		#define TEGRA234_MEMORY_CLIENT_PCIE10AR1 0x48
		/* PCIE7r1 read clients */
		#define TEGRA234_MEMORY_CLIENT_PCIE7AR1 0x49
		/* MGBE0 read client */
		#define TEGRA234_MEMORY_CLIENT_MGBEARD 0x58
		/* MGBEB read client */
		#define TEGRA234_MEMORY_CLIENT_MGBEBRD 0x59
		/* MGBEC read client */
		#define TEGRA234_MEMORY_CLIENT_MGBECRD 0x5a
		/* MGBED read client */
		#define TEGRA234_MEMORY_CLIENT_MGBEDRD 0x5b
		/* MGBE0 write client */
		#define TEGRA234_MEMORY_CLIENT_MGBEAWR 0x5c
		/* MGBEB write client */
		#define TEGRA234_MEMORY_CLIENT_MGBEBWR 0x5f
		/* MGBEC write client */
		#define TEGRA234_MEMORY_CLIENT_MGBECWR 0x61
		/* sdmmcd memory read client */
		#define TEGRA234_MEMORY_CLIENT_SDMMCRAB 0x63
		/* MGBED write client */
		#define TEGRA234_MEMORY_CLIENT_MGBEDWR 0x65
		/* sdmmcd memory write client */
		#define TEGRA234_MEMORY_CLIENT_SDMMCWAB 0x67
		/* BPMP read client */