Commit 8ca2a81b authored by Siddharth Vadapalli's avatar Siddharth Vadapalli Committed by Vinod Koul
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dt-bindings: phy: ti: phy-gmii-sel: Add bindings for J721e 



TI's J721e SoC supports additional PHY modes like QSGMII and SGMII
that are not supported on earlier SoCs. Add a compatible for it.

Extend ti,qsgmii-main-ports property to support selection of upto
two main ports at once across the two QSGMII interfaces.

Signed-off-by: default avatarSiddharth Vadapalli <s-vadapalli@ti.com>
Reviewed-by: default avatarRob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20221026074532.109220-2-s-vadapalli@ti.com


Signed-off-by: default avatarVinod Koul <vkoul@kernel.org>
parent 0f607406

Documentation/devicetree/bindings/phy/ti,phy-gmii-sel.yaml

+42 −6
Original line number Diff line number Diff line
@@ -54,6 +54,7 @@ properties: 
      - ti,dm814-phy-gmii-sel

      - ti,am654-phy-gmii-sel

      - ti,j7200-cpsw5g-phy-gmii-sel

      - ti,j721e-cpsw9g-phy-gmii-sel



  reg:

    maxItems: 1
@@ -63,14 +64,17 @@ properties: 
  ti,qsgmii-main-ports:

    $ref: /schemas/types.yaml#/definitions/uint32-array

    description: |

      Required only for QSGMII mode. Array to select the port for

      QSGMII main mode. Rest of the ports are selected as QSGMII_SUB

      ports automatically. Any one of the 4 CPSW5G ports can act as the

      main port with the rest of them being the QSGMII_SUB ports.

    maxItems: 1

      Required only for QSGMII mode. Array to select the port/s for QSGMII

      main mode. The size of the array corresponds to the number of QSGMII

      interfaces and thus, the number of distinct QSGMII main ports,

      supported by the device. If the device supports two QSGMII interfaces

      but only one QSGMII interface is desired, repeat the QSGMII main port

      value corresponding to the QSGMII interface in the array.

    minItems: 1

    maxItems: 2

    items:

      minimum: 1

      maximum: 4

      maximum: 8



allOf:

  - if:
@@ -81,12 +85,43 @@ allOf: 
              - ti,dra7xx-phy-gmii-sel

              - ti,dm814-phy-gmii-sel

              - ti,am654-phy-gmii-sel

              - ti,j7200-cpsw5g-phy-gmii-sel

              - ti,j721e-cpsw9g-phy-gmii-sel

    then:

      properties:

        '#phy-cells':

          const: 1

          description: CPSW port number (starting from 1)



  - if:

      properties:

        compatible:

          contains:

            enum:

              - ti,j7200-cpsw5g-phy-gmii-sel

    then:

      properties:

        ti,qsgmii-main-ports:

          maxItems: 1

          items:

            minimum: 1

            maximum: 4



  - if:

      properties:

        compatible:

          contains:

            enum:

              - ti,j721e-cpsw9g-phy-gmii-sel

    then:

      properties:

        ti,qsgmii-main-ports:

          minItems: 2

          maxItems: 2

          items:

            minimum: 1

            maximum: 8



  - if:

      not:

        properties:
@@ -94,6 +129,7 @@ allOf: 
            contains:

              enum:

                - ti,j7200-cpsw5g-phy-gmii-sel

                - ti,j721e-cpsw9g-phy-gmii-sel

    then:

      properties:

        ti,qsgmii-main-ports: false