Commit 8e340e75 authored by Lad Prabhakar's avatar Lad Prabhakar Committed by Geert Uytterhoeven
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arm64: dts: renesas: r8a774e1: Add CAN[FD] support 



Add CAN[01] and CANFD support to RZ/G2H (R8A774E1) SoC specific dtsi.

Signed-off-by: default avatarLad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: default avatarMarian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com>
Link: https://lore.kernel.org/r/1594811350-14066-21-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com


Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
parent 96ebdb7a

arch/arm64/boot/dts/renesas/r8a774e1.dtsi

+53 −3
Original line number Diff line number Diff line
@@ -34,6 +34,13 @@ audio_clk_c: audio_clk_c { 
		clock-frequency = <0>;

	};



	/* External CAN clock - to be overridden by boards that provide it */

	can_clk: can {

		compatible = "fixed-clock";

		#clock-cells = <0>;

		clock-frequency = <0>;

	};



	cluster0_opp: opp_table0 {

		compatible = "operating-points-v2";

		opp-shared;
@@ -1139,17 +1146,60 @@ avb: ethernet@e6800000 { 
		};



		can0: can@e6c30000 {

			compatible = "renesas,can-r8a774e1",

				     "renesas,rcar-gen3-can";

			reg = <0 0xe6c30000 0 0x1000>;

			interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&cpg CPG_MOD 916>,

				 <&cpg CPG_CORE R8A774E1_CLK_CANFD>,

				 <&can_clk>;

			clock-names = "clkp1", "clkp2", "can_clk";

			assigned-clocks = <&cpg CPG_CORE R8A774E1_CLK_CANFD>;

			assigned-clock-rates = <40000000>;

			power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;

			resets = <&cpg 916>;

			status = "disabled";



			/* placeholder */

		};



		can1: can@e6c38000 {

			compatible = "renesas,can-r8a774e1",

				     "renesas,rcar-gen3-can";

			reg = <0 0xe6c38000 0 0x1000>;

			interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&cpg CPG_MOD 915>,

				 <&cpg CPG_CORE R8A774E1_CLK_CANFD>,

				 <&can_clk>;

			clock-names = "clkp1", "clkp2", "can_clk";

			assigned-clocks = <&cpg CPG_CORE R8A774E1_CLK_CANFD>;

			assigned-clock-rates = <40000000>;

			power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;

			resets = <&cpg 915>;

			status = "disabled";

		};



			/* placeholder */

		canfd: can@e66c0000 {

			compatible = "renesas,r8a774e1-canfd",

				     "renesas,rcar-gen3-canfd";

			reg = <0 0xe66c0000 0 0x8000>;

			interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&cpg CPG_MOD 914>,

				 <&cpg CPG_CORE R8A774E1_CLK_CANFD>,

				 <&can_clk>;

			clock-names = "fck", "canfd", "can_clk";

			assigned-clocks = <&cpg CPG_CORE R8A774E1_CLK_CANFD>;

			assigned-clock-rates = <40000000>;

			power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;

			resets = <&cpg 914>;

			status = "disabled";



			channel0 {

				status = "disabled";

			};



			channel1 {

				status = "disabled";

			};

		};



		pwm0: pwm@e6e30000 {