Loading drivers/gpu/drm/nouveau/include/nvif/cl006b.h 0 → 100644 +11 −0 Original line number Diff line number Diff line #ifndef __NVIF_CL006B_H__ #define __NVIF_CL006B_H__ struct nv03_channel_dma_v0 { __u8 version; __u8 chid; __u8 pad02[2]; __u32 offset; __u64 pushbuf; }; #endif drivers/gpu/drm/nouveau/include/nvif/cl506e.h 0 → 100644 +12 −0 Original line number Diff line number Diff line #ifndef __NVIF_CL506E_H__ #define __NVIF_CL506E_H__ struct nv50_channel_dma_v0 { __u8 version; __u8 chid; __u8 pad02[6]; __u64 vm; __u64 pushbuf; __u64 offset; }; #endif drivers/gpu/drm/nouveau/include/nvif/cl506f.h 0 → 100644 +13 −0 Original line number Diff line number Diff line #ifndef __NVIF_CL506F_H__ #define __NVIF_CL506F_H__ struct nv50_channel_gpfifo_v0 { __u8 version; __u8 chid; __u8 pad02[2]; __u32 ilength; __u64 ioffset; __u64 pushbuf; __u64 vm; }; #endif drivers/gpu/drm/nouveau/include/nvif/cl826e.h 0 → 100644 +14 −0 Original line number Diff line number Diff line #ifndef __NVIF_CL826E_H__ #define __NVIF_CL826E_H__ struct g82_channel_dma_v0 { __u8 version; __u8 chid; __u8 pad02[6]; __u64 vm; __u64 pushbuf; __u64 offset; }; #define G82_CHANNEL_DMA_V0_NTFY_UEVENT 0x00 #endif drivers/gpu/drm/nouveau/include/nvif/cl826f.h 0 → 100644 +15 −0 Original line number Diff line number Diff line #ifndef __NVIF_CL826F_H__ #define __NVIF_CL826F_H__ struct g82_channel_gpfifo_v0 { __u8 version; __u8 chid; __u8 pad02[2]; __u32 ilength; __u64 ioffset; __u64 pushbuf; __u64 vm; }; #define G82_CHANNEL_GPFIFO_V0_NTFY_UEVENT 0x00 #endif Loading
drivers/gpu/drm/nouveau/include/nvif/cl006b.h 0 → 100644 +11 −0 Original line number Diff line number Diff line #ifndef __NVIF_CL006B_H__ #define __NVIF_CL006B_H__ struct nv03_channel_dma_v0 { __u8 version; __u8 chid; __u8 pad02[2]; __u32 offset; __u64 pushbuf; }; #endif
drivers/gpu/drm/nouveau/include/nvif/cl506e.h 0 → 100644 +12 −0 Original line number Diff line number Diff line #ifndef __NVIF_CL506E_H__ #define __NVIF_CL506E_H__ struct nv50_channel_dma_v0 { __u8 version; __u8 chid; __u8 pad02[6]; __u64 vm; __u64 pushbuf; __u64 offset; }; #endif
drivers/gpu/drm/nouveau/include/nvif/cl506f.h 0 → 100644 +13 −0 Original line number Diff line number Diff line #ifndef __NVIF_CL506F_H__ #define __NVIF_CL506F_H__ struct nv50_channel_gpfifo_v0 { __u8 version; __u8 chid; __u8 pad02[2]; __u32 ilength; __u64 ioffset; __u64 pushbuf; __u64 vm; }; #endif
drivers/gpu/drm/nouveau/include/nvif/cl826e.h 0 → 100644 +14 −0 Original line number Diff line number Diff line #ifndef __NVIF_CL826E_H__ #define __NVIF_CL826E_H__ struct g82_channel_dma_v0 { __u8 version; __u8 chid; __u8 pad02[6]; __u64 vm; __u64 pushbuf; __u64 offset; }; #define G82_CHANNEL_DMA_V0_NTFY_UEVENT 0x00 #endif
drivers/gpu/drm/nouveau/include/nvif/cl826f.h 0 → 100644 +15 −0 Original line number Diff line number Diff line #ifndef __NVIF_CL826F_H__ #define __NVIF_CL826F_H__ struct g82_channel_gpfifo_v0 { __u8 version; __u8 chid; __u8 pad02[2]; __u32 ilength; __u64 ioffset; __u64 pushbuf; __u64 vm; }; #define G82_CHANNEL_GPFIFO_V0_NTFY_UEVENT 0x00 #endif