Commit 8f118f61 authored by Nava kishore Manne's avatar Nava kishore Manne Committed by Greg Kroah-Hartman
Browse files

firmware: xilinx: Add pm api function for PL config reg readback 



Adds PM API for performing Programmable Logic(PL) configuration
register readback. It provides an interface to the firmware(pmufw)
to readback the FPGA configuration register.

Signed-off-by: default avatarNava kishore Manne <nava.kishore.manne@amd.com>
Acked-by: default avatarXu Yilun <yilun.xu@intel.com>
Link: https://lore.kernel.org/r/20230224120738.329416-2-nava.kishore.manne@amd.com


Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent 1a0aae88

drivers/firmware/xilinx/zynqmp.c

+33 −0
Original line number Diff line number Diff line
@@ -971,6 +971,39 @@ int zynqmp_pm_fpga_get_status(u32 *value) 
}

EXPORT_SYMBOL_GPL(zynqmp_pm_fpga_get_status);



/**

 * zynqmp_pm_fpga_get_config_status - Get the FPGA configuration status.

 * @value: Buffer to store FPGA configuration status.

 *

 * This function provides access to the pmufw to get the FPGA configuration

 * status

 *

 * Return: 0 on success, a negative value on error

 */

int zynqmp_pm_fpga_get_config_status(u32 *value)

{

	u32 ret_payload[PAYLOAD_ARG_CNT];

	u32 buf, lower_addr, upper_addr;

	int ret;



	if (!value)

		return -EINVAL;



	lower_addr = lower_32_bits((u64)&buf);

	upper_addr = upper_32_bits((u64)&buf);



	ret = zynqmp_pm_invoke_fn(PM_FPGA_READ,

				  XILINX_ZYNQMP_PM_FPGA_CONFIG_STAT_OFFSET,

				  lower_addr, upper_addr,

				  XILINX_ZYNQMP_PM_FPGA_READ_CONFIG_REG,

				  ret_payload);



	*value = ret_payload[1];



	return ret;

}

EXPORT_SYMBOL_GPL(zynqmp_pm_fpga_get_config_status);



/**

 * zynqmp_pm_pinctrl_request - Request Pin from firmware

 * @pin: Pin number to request

include/linux/firmware/xlnx-zynqmp.h

+11 −0
Original line number Diff line number Diff line
@@ -71,6 +71,10 @@ 
#define XILINX_ZYNQMP_PM_FPGA_FULL	0x0U

#define XILINX_ZYNQMP_PM_FPGA_PARTIAL	BIT(0)



/* FPGA Status Reg */

#define XILINX_ZYNQMP_PM_FPGA_CONFIG_STAT_OFFSET	7U

#define XILINX_ZYNQMP_PM_FPGA_READ_CONFIG_REG		0U



/*

 * Node IDs for the Error Events.

 */
@@ -124,6 +128,7 @@ enum pm_api_id { 
	PM_CLOCK_GETRATE = 42,

	PM_CLOCK_SETPARENT = 43,

	PM_CLOCK_GETPARENT = 44,

	PM_FPGA_READ = 46,

	PM_SECURE_AES = 47,

	PM_FEATURE_CHECK = 63,

};
@@ -519,6 +524,7 @@ int zynqmp_pm_aes_engine(const u64 address, u32 *out); 
int zynqmp_pm_sha_hash(const u64 address, const u32 size, const u32 flags);

int zynqmp_pm_fpga_load(const u64 address, const u32 size, const u32 flags);

int zynqmp_pm_fpga_get_status(u32 *value);

int zynqmp_pm_fpga_get_config_status(u32 *value);

int zynqmp_pm_write_ggs(u32 index, u32 value);

int zynqmp_pm_read_ggs(u32 index, u32 *value);

int zynqmp_pm_write_pggs(u32 index, u32 value);
@@ -725,6 +731,11 @@ static inline int zynqmp_pm_fpga_get_status(u32 *value) 
	return -ENODEV;

}



static inline int zynqmp_pm_fpga_get_config_status(u32 *value)

{

	return -ENODEV;

}



static inline int zynqmp_pm_write_ggs(u32 index, u32 value)

{

	return -ENODEV;